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Message started by Vabzter on Feb 7^th, 2007, 11:16pm

Title: Help on opamp design
Post by Vabzter on Feb 7^th, 2007, 11:16pm

Hi all,
I am new to analog design as was wondering how do experienced analog designers design their circuits. For e.g take a 2 stage opamp...

1. In school they gave us the process parameters(un,cox,vth,..) for .35um process. But if you are designing for 90nm technology how to find these values.One way I know is to put the transistor in triode region and plot Id vs Vgs.I get the slope from that graph and by this eqn Slope = k * W/L* Vds I can find the value of k. Is this method correct?

2. How to design if one does not know un,Cox values?

3. Is there any generalized method to design a 2 stage opamp?

Thanks
BR
Vabzter

Title: Re: Help on opamp design
Post by Croaker on Feb 8^th, 2007, 5:13am

The short answer is that none of the square-law equations work, but you can use them to figure out the basic operating principles. Small-signal stuff is always true for design, but you need a simulator to get actual values, e.g. ro, gm.

CMOS Analog Design by Allen has a general procedure. That might be useful, but having a detailed spec is the starting point.

Title: Re: Help on opamp design
Post by topquark on Feb 8^th, 2007, 6:00am

Also, take a look at Berkeley's course
http://bwrc.eecs.berkeley.edu/classes/ee140/

You've also got webcast lectures where there's a nice discussion of a real-world project- a 2-stage op amp design.
It goes through all practical stuff including simulator pitfalls, hand calculations and design trade-offs

Good Luck!

Gau

Title: Re: Help on opamp design
Post by Vabzter on Feb 8^th, 2007, 7:23am

Hi,
Thanks for the replies..But still I am not sure how to find the values of k(=un*Cox) for a perticular technology as we need these values for doing hand calculations..
BR
Vabzter

Title: Re: Help on opamp design
Post by RobG on Feb 8^th, 2007, 10:29am

Vabzter wrote on Feb 8^th, 2007, 7:23am:

Hi,
Thanks for the replies..But still I am not sure how to find the values of k(=un*Cox) for a perticular technology as we need these values for doing hand calculations..
BR
Vabzter

I don't worry about those things... You can do a lot by simply knowing that gm=2*I/Vod, where Vod=(Vgs-Vt). You don't need to know what K' or Vt is to tune Vgs-Vt.... if it is too big, make the devices wider or lengths shorter. You can get Vgs-Vt from the DC operating point information. Vdsat is close to the same quantity -- it is what I usually look at. Hand calculations that use more than Gm have limited use in the design process.... everything interesting is determined by parasitics or nonideal effects (plus Vt and K' change depending on operating point, sizes, etc).

Opamp design is pretty simple (ok, that is a gross exageration).... You give the diff pair high gm, and the load (current mirror) low gm. If you don't, you get a bad op-amp. End of story ;-).

For a given current, all you can do is change Vod. 150mV is a reasonable target for Vod for the diff pair. Lower than that, the diff pair gets into weak inversion and wider widths offer only small improvements (i.e. diminishing returns). 2-400mV is a good target for the mirrors. Since Vod =~ Vdsat, the upper limit is usually set by the amount of headroom you have.

From that basic starting point you can play with the sizes to suit your particular situation (keeping current fixed and lengths as small as you can). If your diff pair is causing frequency response problems you need to make it smaller, which will likely decrease gm (because Vod is increased). Similarly, making the mirrors smaller (increasing Vod) will increase their frequency response (lower Cgs), but it may make other problems - like headroom or an inability to drive cap loads. If you cannot fix things by changing Vod, your only other choice is to increase current (or change topologies).

That said, the first thing I do when I get a new process is to plot the Vt vs. Width for various lengths of devices. You get the Vt information from the DC operating point (just diode connect the devices and put 1uA thru them and do a parametric anlysis sweeping width and length). You will find that Vt is a strong function of length and width for smaller geometries. It is also instructive to plot gm/I vs Vgs-Vt for various sized devices, as well as Vt vs bulk-source voltage. Armed with a few of these plots you can get most of the information you need. Note that, in some sense, this is determining K' and other parameters, but since they are functinos of device sizes it put them in a more usable format.

rg

Title: Re: Help on opamp design
Post by mg777 on Feb 9^th, 2007, 5:47am

RobG, thanks for the succint and illuminating tutorial on op-amp design. In particular I liked the relation between g_m and headroom.

I once read an IEEE JSSC (Red Journal) paper that showed how an op-amp's A_d, CMRR, and PSRR are mutually related by trade-offs. Anyone remember this paper, or an equivalent reference?

M.G.Rajan
www.eecalc.com

Title: Re: Help on opamp design
Post by Vabzter on Feb 12^th, 2007, 2:23am

RobG wrote on Feb 8^th, 2007, 10:29am:

Vabzter wrote on Feb 8^th, 2007, 7:23am:

Hi,
Thanks for the replies..But still I am not sure how to find the values of k(=un*Cox) for a perticular technology as we need these values for doing hand calculations..
BR
Vabzter

Hi RobG
Thanks for the comprehensive guide to design. It certainly cleared most of my doubts. One more question..I want to drive a 35pF load at the output of opamp. The current consumption should be less and in range of 50uA. Which config should I use..will a simple 2 stage amplifier work or should I go for Folded Casode one? The supply is 1.8V.
Thanks a lot for your help
BR
Vabzter

Title: Re: Help on opamp design
Post by panditabupesh on Feb 13^th, 2007, 8:02am

Whether to use a two-stage or folded-cascode Opamp depends upon the output swing you want from the Opamp. You can not have rail-to-rail swing from a single-stage Opamp, also the folded-cascode Opamp will have higher power dissipation. An advantage of using folded-cascode would be that it can be compensated by the load capacitor - that makes it easier to behave.

Bupesh

Title: Re: Help on opamp design
Post by Croaker on Feb 13^th, 2007, 9:46am

The folded-cascode amplifier is useful for increasing the ICMR.

Title: Re: Help on opamp design
Post by RobG on Feb 15^th, 2007, 1:55pm

Quote:

sorry for the delay... I've been out of town at ISSCC.... Assuming you are only driving cap loads, tell me the bandwidth you are looking for, and I'll show you how I'd go about solving the problem.

Title: Re: Help on opamp design
Post by RobG on Feb 15^th, 2007, 2:01pm

mg777 wrote on Feb 9^th, 2007, 5:47am:

I once read an IEEE JSSC (Red Journal) paper that showed how an op-amp's A_d, CMRR, and PSRR are mutually related by trade-offs. Anyone remember this paper, or an equivalent reference?

You are probably referring to the tutorial by Grey and Meyer in the Dec. 1982 issue of JSSC. Every month this article seems to still make the top 100 IEEE most downloaded article list even after 25 years. It is definately a must read: Click Here for article.

Rog

Title: Re: Help on opamp design
Post by Vabzter on Feb 16^th, 2007, 6:24am

RobG wrote on Feb 15^th, 2007, 1:55pm:

Quote:

sorry for the delay... I've been out of town at ISSCC.... Assuming you are only driving cap loads, tell me the bandwidth you are looking for, and I'll show you how I'd go about solving the problem.

Hi RobG,
The bandwidth should be around 10Mhz. The application is it should drive a 35pF load and output must be 1.75V. It is connected to output of DAC which has output of 1.2V(for full 10bit digital input). So the amplification in closed loop should be around 1.5. I have designed a 2 stage amplifier but getting a open loop gain of 35(very low). So I was thinking which is the configuration to use in case I want to drive a large capacitive load.
Thanks a lot for your help,
BR
Vabzter

Title: Re: Help on opamp design
Post by MTXamp on Feb 17^th, 2007, 8:53pm

Hi Vabzter

The simplest and quickest way of obtaining k' is to look at your model files. If you are using spectre, you can locate your model files using the menu in the simulator's window: Setup -> Model files

k' = uCox. "u" is already given in the model file as "u0". Cox can be calculated using:

Cox = (er)(e0)/tox

er = relative permittivity of SiO2 = approx 3.9
e0 = 8.854x10e-12
tox = give in model file as "tox"

An opamp design always starts with the selection of the topology. Everything follows after that. Your specs seems quite tough: 10MHz bandwidth, drives a 35pF load, large output swing but yet the current consumption has to be about 50uA. Is it possible? : ) Seems quite a challenge to me. The book "Design of low voltage, low power operational amplifier cells" by Ron Hogervorst and Johan H Huijsing(Publisher: Kluwer Academic) might be useful for you.

Hope that this is useful for you.

Best regards
Quek

Title: Re: Help on opamp design
Post by robfox68 on Feb 18^th, 2007, 7:12am

Do a fundamental calculation before you start. The bandwidth of any amplifier cannot exceed gm/CL. If all of your 50 uA bias current was used in a BJT, the transconductance would be Ic/Vth = 2 mA/V at room temperature. With CL = 35 pF, this gives 60 Mr/s, less than 10 MHz. The transconductance of a FET is always lower than that of a BJT for the same bias current.

Your specifications are not realizable.

Title: Re: Help on opamp design
Post by Vabzter on Feb 19^th, 2007, 2:42am

MTXamp wrote on Feb 17^th, 2007, 8:53pm:

Hi Quek,
Yes I had tried before with the model files but the results were not matching the simulation plots..
For the opamp I guess I have to decrease the bandwidth as I am going to use it to drive a 35pF load. The critical parameter is current consumption..
Thanks a lot for your help,
BR
Vabzter

Title: Re: Help on opamp design
Post by Vabzter on Feb 19^th, 2007, 2:45am

robfox68 wrote on Feb 18^th, 2007, 7:12am:

Hi Robfox68,
Thats a good check go a feasible design..Thanks a lot for this tip. I guess I have to decrease the bandwidth.
BR
Vabzter

Title: Re: Help on opamp design
Post by RobG on Feb 19^th, 2007, 11:47am

Vabzter,
I agree with the other posters -- it will be difficult to achieve that bandwidth with that load cap and total current.

Here is how you can quickly see that by simply knowing that gm≈2*I/Vod, where Vod=Vgs-Vt if we are in strong inversion. (In weak inversion gm≈ 2*I/(100mV); that is, you can't invcrease gm by making Vgs-Vt < 100mV).

We know for a single stage amplifier (folded cascode, telescopic, etc), the bandwidth is gm/(2*pi*C) (where gm is 2*I/Vod of one side of the diff pair). In this case, the required gm is (2*pi*10MHz)*35pF = 2.2mA/V. Thus, we need a Vod=2*25uA/(2.2mA/V) = 23mV. This is impossible - remember Vod limits to about 100mV when the devices get into subthreshold.

A more reasonable assumption of Vod=150mV limits your bandwidth to (2*25uA)/(2*pi*35pF*0.15) = 1.5MHz.

Note I've assumed nothing about process.... just that gm ≈2*I/Vod, where Vod = Vgs-Vt in strong inversion, and 100mV in weak inversion.

You can do a similar analysis for a two stage (e.g miller compensated) and show that your non-dominant pole will be around gm/Cload, so even if you can get the bandwidth, you won't have phase margin unless you put a zero in the system - which will create doublets (read Kameth, Grey, Meyer, "Relationship between frequency response and settling time of operation amplifiers," JSSC, Dec 1974). While you can cheat a little here... you need to gain a factor of 10 in bandwidth.... I don't think you can do it and drive that load.

Rob

Title: Re: Help on opamp design
Post by Vabzter on Feb 20^th, 2007, 1:19am

RobG wrote on Feb 19^th, 2007, 11:47am:

Hi Rob,
Thanks for giving a simplified explaination..Well so I have formed new specs for the opamp.
Bw=1MHz,
Vout =1.7V,
Vdd=1.8V,
Idc(max)=50uA,
Cl=35pF,Rl=5Kohm,

So with these specs I tried to design a simple 2 stage opamp. I am getting an open loop gain of 40dB(very less). The phase margin is 80•.

My application is it should amplify the voltage at ouput of DAC whose full scale output is 1.2V.

So I am not getting whether I should use a 2 stage simple opamp of Cascode one..What is the criteria for selecting the topology?

Thanks a lot for your help,
BR
Vabzter

Title: Re: Help on opamp design
Post by MTXamp on Feb 20^th, 2007, 5:59am

Hi Vabzter

Imho, your spec still seems quite tough to me. Since your Vdd is 1.8V, if I assume that your load resistor of 5K is going to be tied to 1/2Vdd of 0.9V...in order for the voltage to rise to 1.7V under DC conditions, your output stage would have to source out at least (1.7-0.9)/5K=160uA. Is this ok for you? This has not even taken into account the current that is going to flow in your feedback path, assuming that you are going to use a non-inverting configuration. With the 1MHz added in, you will most probably run into slew rate problem.

Although your BW has now been reduced to 1MHz, your load res and cap will still pose a big problem. I feel that 50uA is not going to get you through the typical and corner conditions.

A simple miller's opamp will most probably not be able to get the job done. If you were to use the classAB output as discussed in Hujsing's book, you will need more than 50uA at the output stage in order to stabilize the circuit.

My 2 cents worth. ;)

Best regards
Quek

Title: Re: Help on opamp design
Post by RobG on Feb 20^th, 2007, 11:11am

Vabzter wrote on Feb 20^th, 2007, 1:19am:

As MTXamp stated, this is still a tough design. The resistive load changes everything: you need an output stage to supply the DC current, so you are stuck with at least two stages. It is impossible to say which topology will work best for you -- op-amp design is a bit of an art, not a recipe. But I'd start with a Miller two stage amplifier with an NMOS diff-pair and PMOS output stage. If the 5k-ohm is fixed, it will act to bias the PMOS output stage nicely. Once you understand the Miller design, you may want to try other designs, such as using a folded cascode input stage, and a PMOS output stage.

rg

Title: Re: Help on opamp design
Post by RobG on Feb 20^th, 2007, 11:14am

In addition to the resistive load, the output voltage being only 100mV from the power supply will be very challenging - you will get very little gain from your output stage.

Title: Re: Help on opamp design
Post by eng on Apr 3^rd, 2007, 1:38pm

Hi all,
I'm working on a similar circuit(fully diff). The replies were very useful for me. Thank you so much.
I have a question about the testbench of opamp. I see in some of the test benches that the bottom plate of load capacitor is connected to common mode voltage. (i.e. if vdd=1.8 and vss=0 and CM=.5 ; botton plate of load is connected to CM)

What is the reasoning behind it?

Title: Re: Help on opamp design
Post by ywguo on Apr 6^th, 2007, 1:52am

Hi, eng,

I think that configuration doesn't affect the function of the opamp. It get the same result as that the bottom plate is tied to gnd if you run ac simulation. Normally the fully differential amp has cmfb so that it doesn't matter where the bottom plate is tied to.

Yawei

Title: Re: Help on opamp design
Post by imd1 on Apr 10^th, 2007, 1:14am

If you connect the bottom plate of the load capacitor to the CM voltage there can be a bootstrapping effect. Is it connected to a voltage source,
or is it driven by a VCVS, so it follows the output of the common-mode feedback circuit ?

Title: Re: Help on opamp design
Post by eng on Apr 12^th, 2007, 10:29am

Here is the thing;
Since the purpose of simulation is to mimic the real environment, the output stage should be able to sink the same amount of the current from the load as well as it sources to it. When I looked at old opamp circuits the loads are grounded but these circuits have vdd and vss (=-vdd) and VoutCM is zero. The question is with a single supply should we connect them to Vdd/2 or CM(assuming they're different)?

imd1: Using VCVS seems a good idea but do you think even if we use fix CM bootstrapping actually happens and it affects the CMout?

Title: Re: Help on opamp design
Post by buckaroo on Apr 23^rd, 2007, 10:02am

well done ;D

RobG wrote on Feb 8^th, 2007, 10:29am:

Vabzter wrote on Feb 8^th, 2007, 7:23am:

Hi,
Thanks for the replies..But still I am not sure how to find the values of k(=un*Cox) for a perticular technology as we need these values for doing hand calculations..
BR
Vabzter