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Design Languages >> Verilog-AMS >> Solving an implicit equation
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Message started by VerilogANovice on Feb 11^th, 2007, 6:03pm

Title: Solving an implicit equation
Post by VerilogANovice on Feb 11^th, 2007, 6:03pm

Hi,

Is there any way in Verilog-A to solve an implicit equation? The function I want it to peform is like "fzero" in MATLAB.

Title: Re: Solving an implicit equation
Post by Ken Kundert on Feb 12^th, 2007, 12:28am

Yes, of course. All contributions can be implicit. In this case they are written in fixed point form: x=f(x). Verilog-A also provided the indirect assignment statement that explicitly supports implicit formulations. ;)

-Ken

Title: Re: Solving an implicit equation
Post by VerilogANovice on Feb 12^th, 2007, 1:34am

Thanks! A follow-up question: What if the equation has multiple solution? Is there anyway I can specify the range of the root?

Title: Re: Solving an implicit equation
Post by Ken Kundert on Feb 12^th, 2007, 3:01pm

Not in Verilog-A, but most simulators support a nodeset capability that allows you to bias the simulator towards finding one particular solution.

-Ken