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Design >> Mixed-Signal Design >> Relation between DNL,resistive ladder mismatch...
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Message started by Vabzter on Feb 16^th, 2007, 6:44am

Title: Relation between DNL,resistive ladder mismatch...
Post by Vabzter on Feb 16^th, 2007, 6:44am

Hello everyone,
I trying to find a relation between DNL and elemental mismatch for a resistive ladder dac. I know that the worst case DNL is when the ladder position is at the end. In my case there are 2 ladders..
I have got a relation between INL and mismatch but dont know how to go about finding a relation between DNL and elemental mismatch..
Any help or reference material which I can use..
Thanks a lot in advance
BR
Vabzter

Title: Re: Relation between DNL,resistive ladder mismatch
Post by panditabupesh on Feb 16^th, 2007, 7:36am

Hello
Razavi in 'Principles of Data Conversion System Design', chap 4, has given a bunch of relations relating DNL with resistance mismatch.

Bupesh

Title: Re: Relation between DNL,resistive ladder mismatch
Post by Vabzter on Feb 16^th, 2007, 8:01am

panditabupesh wrote on Feb 16^th, 2007, 7:36am:

Hello
Razavi in 'Principles of Data Conversion System Design', chap 4, has given a bunch of relations relating DNL with resistance mismatch.

Bupesh

Hi Bhupesh
Yup I have gone through them. What I am looking for is relation between σ and DNL. In those relations he has derived that the max DNL is at the 2 ends and max INL is in the middle position of the ladder. I want the relation to size the resistive ladder in dac
Thanks
BR
Vabzter

Title: Re: Relation between DNL,resistive ladder mismatch
Post by panditabupesh on Feb 16^th, 2007, 11:40am

This is from the JSSC paper, " A 10-bit 5-Msample/s ...." by Doernberg, Gray, and Hodges- relationship (6)

(sigmaR)/R = 2^[(n-1)/(2-N)].
Now sigmaR/R = r_alpha/sqrt(WL); r_alpha is the mismatch parameter supplied by the foundry.

Am I missing something?

Bupesh

Title: Re: Relation between DNL,resistive ladder mismatch
Post by Vabzter on Feb 18^th, 2007, 11:08pm

panditabupesh wrote on Feb 16^th, 2007, 11:40am:

Hi Bupesh,
Yup the above equation is right. I have also got the value of r_alpha from the reference manual from the foundry. The question is I am designing a 10 bit ladder DAC and I want to derive a relation between the DNL and mismatch.Then by using the above equation I can size the resistance values. Like for INL I found this relation from Berkeley site for the leactures on Data converters(references are not mentioned on the leacture slides...)..
B = 2 + 2log2(σ_inl / σ_mis) .......(log2 = log to base 2, B=no. of bits)

So in the similar manner I want to find a relation between DNL and mismatch..

Thanks for your help
BR
Vabzter

Title: Re: Relation between DNL,resistive ladder mismatch
Post by Vabzter on Feb 19^th, 2007, 12:50am

panditabupesh wrote on Feb 16^th, 2007, 11:40am:

Hi Bupesh
One more question..In the above formula n = Resolution in bits and n = linearity in no. of bits..So what is the relation between them?
Thanks
BR
Vabzter

Title: Re: Relation between DNL,resistive ladder mismatch
Post by panditabupesh on Feb 20^th, 2007, 8:22am

Hello
Though the paper uses terms like precision and linearity for N, but I think it means same as accuracy. For example let us consider an 8-bit two-step (or subranging) ADC, and we are extracting 4-bit MSBs and 4-LSBs in two steps. Without digital-error correction, even though we are extracting only 4-bit MSBs (resolution n= 4) the DAC ( a resistance ladder etc ) involved will need to be 8-bit accurate (linearity N = 8). But, for a single-step 8-bit ADC, e.g flash, the resolution and accuracy will be same and equal to 8-bits.

Johns & Martin spend a couple of pages, section 13.5, on this topic.

bye
Bupesh