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Simulators >> AMS Simulators >> "System Verilog" import
https://designers-guide.org/forum/YaBB.pl?num=1171882045

Message started by Pavel on Feb 19^th, 2007, 2:47am

Title: "System Verilog" import
Post by Pavel on Feb 19^th, 2007, 2:47am

Hello,

Is there a possibility to import "System Verilog" code?

Regards

Pavel.

Title: Re: "System Verilog" import
Post by Geoffrey_Coram on Feb 19^th, 2007, 4:38am

Import it into what? A simulator? (Many 1364-Verilog simulators already support portions of the SV extensions.) A schematic editor? (Some tools have a Verilog-in mode so you can try to make sense of Verilog netlists.)

Title: Re: "System Verilog" import
Post by Pavel on Feb 19^th, 2007, 5:01am

As cell in Library Manager to be used as Test Bench.
I tried already Verilog-In. But in System Verilog there are constructs that aren't supported by Verilog/Verilog 2001 parser.
So import didn't pass.

Regards.

Title: Re: "System Verilog" import
Post by zhong on Feb 23^rd, 2007, 12:44am

Pravel ,
You can not import SystemVerilog via VerilogIn today. VerilogIn basically is using ncvlog without -sv option as a paser . Parse/Compile SystemVerilog requires -sv option in ncvlog .
If you want to get SystemVerilog into DFII view , do following

ncvlog -sv -use5x -work mylib my_systemVerilog_file.sv

It will create DFII cell view under mylib.

Zhong

Title: Re: "System Verilog" import
Post by Pavel on Feb 23^rd, 2007, 4:15am

Thanks Zhong,

It worked. Cell was created with module view.

Regards.

Pavel.

Title: Re: "System Verilog" import
Post by Pavel on Feb 23^rd, 2007, 4:42am

Problem is partially resolved.
This command only get cell in Library Manager as module view. When I compile it features specific to System Verilog (for example logic keyword provoke errors.

Should I run some command in icms in order to set System Verilog support for parser?

Regards.

Pavel.

Title: Re: "System Verilog" import
Post by zhong on Feb 25^th, 2007, 8:55pm

There is no special env varible today in GUI flow to handle SystemVerilog.
The problem you have is that ,
you compile the SystemVerilig text into DFII view use -sv --- works fine
After that ,
In AMS-ADE or AMS-HED , the GUI flow will RE-COMPILE the SystemVerilog without -sv option.
---- This explains why you have problem.

The workaround is to
1. Compile all your SystermVeriliog to a exclusive lib which only have SystermVerilog
for example
ncvlog -use5x -sv -work my_systemVerilig_lib my_systemVerilog_file.sv

2. In GUI flow (either AMS-ADE or AMS-HED)
add my_systemVerilog_lib in the "exclude libs list for compilation" . You can find this field in the Compilation option form .
This will avoid GUI re-compile the systemVerilog without -sv option.

BTW, if you change your IUS version , You need to re-do
ncvlog -use5x -sv -work my_systemVerilig_lib my_systemVerilog_file.sv
to ensure the version of IUS you are using in command compilation is same as GUI flow.

Hope this helps ..

Zhong

Title: Re: "System Verilog" import
Post by Pavel on Feb 26^th, 2007, 2:20am

Thank you for answer, Zhong.
If I properly understood, once System Verilog cell is get to HE, I cannot change its code and compile in HE.
I have to use command line.

Regards.

Pavel.

Title: Re: "System Verilog" import
Post by zhong on Feb 26^th, 2007, 9:03pm

Pravel,
Your understand that corretly. As of today, GUI flow default does not issues the -sv for the compilation.

However you can add -sv in the additional compilation option in GUI . Now the issues will be -sv will be apply for all the text file (verilog/SystermVerilog/verilog.vams (generated from schematic) , the problem then is NC does not allow you have co-existence of -sv -ams option in the same ncvlog compilation line. This will cause the compilation failure on verilog.vams netlsit which generated from schemaitc.

What you can do is to
1. Once you have changed the SystemVerilog . Compile that from Command line
or
2. Add -sv in the GUI compilation option ,
then surgically compile the SystemVerilog cell only in HED
after that remove -sv from GUI option, add the systemVerilog lib in the Exclude list
compile all

I would suggest you to go with solution 1>. It's much esaier than 2.

Zhong