The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Read file into verilog-a, can it be done?
https://designers-guide.org/forum/YaBB.pl?num=1171920606

Message started by mattpace on Feb 19^th, 2007, 1:30pm

Title: Read file into verilog-a, can it be done?
Post by mattpace on Feb 19^th, 2007, 1:30pm

Greetings,
I have enjoyed reading and garnered much information from this forum, thank you !!
I find myself now needing to ask, can verilog-a read a file? ( I see fopen & fclose, but no read).
I design CMOS image sensors and to perform a top level simulation I'd like to read a simulated
image in from a file and present it to the image sensor as pixels via verilog-a. The image would be 2 dimensional
so using pwl sources doesn't really work.
Any help will be grealy appreciated
Best regards
Matt at Kodak

Title: Re: Read file into verilog-a, can it be done?
Post by Andrew Beckett on Feb 22^nd, 2007, 11:14am

Yes, using $fopen("filename","r") and $fscanf().

Regards,

Andrew.

Title: Re: Read file into verilog-a, can it be done?
Post by Geoffrey_Coram on Feb 22^nd, 2007, 12:53pm

mattpace wrote on Feb 19^th, 2007, 1:30pm:

( I see fopen & fclose, but no read).

There are some subtle differences between fopen in 1364 Verilog and in Verilog-AMS, that's why it appears in the AMS LRM. The fread in AMS/VerilogA is supposed to be the same as 1364, so it wasn't put in the manual. So, as Andrew wrote, you should be able to use it.

You might also look at $table_model, which might be slightly easier to use.

Title: Re: Read file into verilog-a, can it be done?
Post by DReynolds on Mar 12^th, 2007, 8:27am

Andrew, I tried to use $fscanf in veriloga to read a file, but I get a failure in elaboration

ch' (cds.lib command ignored).
Elaborating the design hierarchy:
Discipline resolution Pass...
Building instance overlay tables: .................... Done
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 3 3
Registers: 20 20
Interconnect: 2 -
Simulation timescale: 1ns
Writing initial simulation snapshot: analogLogic.sim_compute_checker:config
Elaborating analog portion of the design hierarchy:
libsyracuse: @(#)$CDS: libsyracuse version 02/08/2006 23:17 (nclx35) $(sub-version 0208 )
while(!$fscanf(point,"%f %f \n",value,valueb)) begin
|
ncelab: *E,SYFATAL (/dsk3/analoglogic/al2/David/design/dfII/analogLogic/compute_checker/veriloga/veriloga.va,45|16): `$fscanf' - Unsupported system task/function.

Is there something special that has to be included in the model to allow fscanf?
David Reynolds

Error found by spectre.

Title: Re: Read file into verilog-a, can it be done?
Post by Andrew Beckett on Mar 15^th, 2007, 6:53am

Quick answer since I need to rush to a meeting and will probably forget otherwise :-[ - you might have to use $fread in AMS. $fscanf should be supported, but I've not checked...

Regards,

Andrew.

Title: Re: Read file into verilog-a, can it be done?
Post by DReynolds on Mar 22^nd, 2007, 5:53am

Andrew, it turns out that fscanf does not work in veriloga... the pcr is 871309 and there is a new release that is supposed to fix the issue, but I have not had time to try it. I was able to get around it for the time being by writing the contents of the file into a list in skill then printing it out to a file that I stitched into my veriloga.

data[0] =0.335;
data[1] =0.004;
etc

David Reynolds

Title: Re: Read file into verilog-a, can it be done?
Post by Andrew Beckett on Apr 12^th, 2007, 1:30am

Hi David,

Actually it worked in VerilogA in spectre, but it didn't work in AMS Designer. However, that PCR was fixed about a year ago, in IUS57 s1 (the
first ISR of IUS57).

So providing you're using a recent enough build, you should be able to use it now.

Regards,

Andrew.

Title: Re: Read file into verilog-a, can it be done?
Post by ghad on Jul 23^rd, 2007, 1:14pm

Hi,
I have a problem in VerilogA, and I tried to read the posts in the Forum, and I found out that this might be the closest topic...
I need to get the value of a number from a text file, containing only this number.
Then take this value, and use it to increase the voltage of a certain circuit....
I 've tried:

analog begin
file = $fopen("/home/user/myfile.txt","r");
rr = $fscan(file," %f:\n", real_time);
$fclose(file);

But when I do so, it does compile, but doesn't output any waveforms on cadence.
I tried replacing $fscan by $fread. It's doesn't even compile.

Is there any easy code, that can get a number from a text file, so that it can be used in the program?
Thank you in advance.
Best Regards.

Title: Re: Read file into verilog-a, can it be done?
Post by Marq Kole on Jul 23^rd, 2007, 11:55pm

$fread is for binary data, for ASCII data you should use $fscanf. These are strictly speaking not Verilog-AMS 2.2 as they are only defined in the Verilog HDL 1364-2001 standard, section 17.2.4 (Verilog-AMS 2.2 is based on 1364-1995). So check your simulator's supported extensions to Verilog-AMS to see if this works.

Code:

analog begin
file = $fopen("/home/user/myfile.txt", "r");
rr = $fscanf(file, " %f:\n", real_time);
$fclose(file);
end

They are planned to become part of the Verilog-AMS 2.3 standard.