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Design Languages >> Verilog-AMS >> Instantiating a built-in model
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Message started by VerilogANovice on Feb 25^th, 2007, 3:03am

Title: Instantiating a built-in model
Post by VerilogANovice on Feb 25^th, 2007, 3:03am

Hi all,

Can I instantiate a built-in MOS model from Verilog-A?

Thanks

Title: Re: Instantiating a built-in model
Post by zhong on Feb 25^th, 2007, 11:52pm

You can..

Title: Re: Instantiating a built-in model
Post by VerilogANovice on Feb 26^th, 2007, 12:39am

Do you know how to do that in HSPICE? I am not sure how I can read in the model card in Verilog-A.

Title: Re: Instantiating a built-in model
Post by Geoffrey_Coram on Feb 26^th, 2007, 5:23am

The Verilog-AMS LRM does not specify how one defines model cards -- or the "library" for resolving model references -- in a Spice simulator. You'd need to check with an application engineer from Synopsys to find out how this works in HSpice.