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Design >> Analog Design >> pll loop bandwidth
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Message started by sivacharan on Feb 25^th, 2007, 10:23pm

Title: pll loop bandwidth
Post by sivacharan on Feb 25^th, 2007, 10:23pm

if the ref freq to a pll is varying over a big range like 3M to 400M, then how do we choose the loop bandwidth??

some where i read that the loop bandwidth is around 1/10 of the ref freq to avoid cycle slipping. but for a varible ref freq how can we assume a fixed loop bandwidth so that the lock time is same in all the cases??

thanks.

Title: Re: pll loop bandwidth
Post by YeeQ on Feb 27^th, 2007, 6:15pm

I think you can use adaptive PLL.

a reference paper:
"Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techiques" JSSC, Vol 31, Nov. 1996

Title: Re: pll loop bandwidth
Post by mg777 on Feb 27^th, 2007, 9:10pm

Put a freq divider in the feedback loop so that the VCO freq lies is in a small range.

M.G.Rajan
www.eecalc.com

Title: Re: pll loop bandwidth
Post by ywguo on Feb 28^th, 2007, 9:49pm

mg777 wrote on Feb 27^th, 2007, 9:10pm:

Put a freq divider in the feedback loop so that the VCO freq lies is in a small range.

M.G.Rajan
www.eecalc.com

That is useless for that the ref varies over two orders of frequency. The frequency divider in the feedback loop desn't change the ref freq.

Yawei

Title: Re: pll loop bandwidth
Post by vivkr on Mar 1^st, 2007, 1:31am

ywguo wrote on Feb 28^th, 2007, 9:49pm:

mg777 wrote on Feb 27^th, 2007, 9:10pm:

Put a freq divider in the feedback loop so that the VCO freq lies is in a small range.

M.G.Rajan
www.eecalc.com

That is useless for that the ref varies over two orders of frequency. The frequency divider in the feedback loop desn't change the ref freq.

Yawei

Hi Yawei,

I think Rajan is talking about putting a programmable counter in the loop, and changing the %N factor so that the PFD always sees more or less the same update frequency regardless of actual input reference frequency. Am I right Rajan?

Regards
Vivek

Title: Re: pll loop bandwidth
Post by mg777 on Mar 1^st, 2007, 7:43am

Yes Vivek, the key is the programmable counter. The ref freq can be divided as well, the counter can even be made m out of n.

M.G.Rajan
www.eecalc.com

Title: Re: pll loop bandwidth
Post by thlcak on Mar 3^rd, 2007, 8:31pm

Does that mean pll loop bandwidth is equal to the freq. that PFD sees?
I am confused because most of the time I heard from pll designer saying the pll bw around few mhz.

Title: Re: pll loop bandwidth
Post by mg777 on Mar 4^th, 2007, 4:21am

The PLL loop bandwidth determines the update rate of the VCO. In the classical linear analysis under lock, a small loop bandwidth attenuates input jitter but emphasizes the VCO phase noise. In addition, the capture range becomes small and acquisition is slow. A large loop bandwidth means the opposite. So you have a trade-off, which is further complicated by considerations of 1/f noise, loop stability and cycle slipping.

To answer your question, it's not the PFD input frequency that sets the loop bandwidth but the K_v of the VCO (along with K_p, and G_o). Aside of these nice linear considerations, acquisition is a complicated non-linear process. That's why PLL designs tend to be conservative, and also why simulators that provide accurate analysis of PLL transients are required.

The source book for PLL basics has been Gardner. Lee's RF CMOS book has a couple of nice chapters on PLL design. I also like Gray+Meyer's original PLL chapter for its insights.

M.G.Rajan
www.eecalc.com

Title: Re: pll loop bandwidth
Post by fonseca.ha on Mar 6^th, 2007, 4:49am

What is the output frequency that you are trying to cover? You talk about input range, but is the PLL multiplying by a fixed number? or the output range is the same as the input range?

Title: Re: pll loop bandwidth
Post by sivacharan on Mar 6^th, 2007, 9:47pm

very useful replies.
My pll output freq range is 200M to 800M using M,N and P dividers.(N=2- 128,N=1-32 and P=1-2).
Ref freq is 3.125M to 400M and VCO freq is 400M to 800M. supply voltage is 1v.

How can we decide the loop bandwidth??
thanks.

Title: Re: pll loop bandwidth
Post by adesign on Mar 7^th, 2007, 10:22pm

You can use a programmable divider in the feedback loop. Also use a programmable charge-pump also. Thus, I/N will remain constant and hence the loop-bandwidth tracking happens with the reference frequency.

Hope it helps.

Title: Re: pll loop bandwidth
Post by fonseca.ha on Mar 8^th, 2007, 12:21am

For loop bandwidth, thinking about stability, and assuming that phase noise will be dominated by the VCO, you can start by checking what is the minimum required reference frequency.
And that may not be the minimum input frequency has, in case a strange multiplication ratio is needed, the pre-divider may have to divide it down.

Assuming that you have a conventional analog charge-pump pll, looking at the open loop tranfer function, for the above case the GBW should be 10 times smaller than this minimum reference frequency.

When checking the open loop gain, one think that affects it is the feedback multiplication ratio. But normally, for the minimum reference frequency not all feedback multiplication ratios are possible, as the operating limits of the VCO have to be respected.

In your case, if for example for the minimum reference, assuming it is 3.125M, the possible feedback multiplication ratios are: 128...256. I see that for your case N only changes between 2 and 128, so it seems that with the minimum reference frequency, the maximum VCO frequency cannot be generated.

With the above you may design a loop filter.

Now we have to see what happens for the other feedback multiplication ratios,

As the feedback multiplication ratio starts to become smaller the GBW starts to increase. If you look at it, the GBW may increase, because now the minimum reference frequency is also bigger. This because we need to respect the operating limits of the VCO.

But the problem is not so much the GBW increasing, the problem is more you loosing phase margin.

The consequence is that, for smaller 'N' you may need to either make a loop filter resistor that is programable with 'N' so that it traks its variation, or a charge pump current also variable with N.
The difference will be that a programable charge pump will allow a constant GBW, and a programable resistor allows to track the increase in the minimum possible reference frequency.

Hope it helps
Humberto