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Design Languages >> Verilog-AMS >> detecting discrete events in analog contents
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Message started by Pavel on Feb 26^th, 2007, 8:03am

Title: detecting discrete events in analog contents
Post by Pavel on Feb 26^th, 2007, 8:03am

Hello

Is there a simple way to detect in analog block every change of bus discrete signal.
There is event-insensitive code

Code:

logic en;
logic [3:0] Itrim;

real i_total;
localparam i0 = 1u;

analog begin
i_total = (en)?(i0 + (Itrim[0])?i0:0.0 + (Itrim[1])?2*i0:0.0 + (Itrim[2])?4*i0:0.0 + (Itrim[3])?4*i0:0.0):0.0;

When I try transform it in event-sensitive

Code:

@(en or Itrim)
i_total = (en)?(i0 + (Itrim[0])?i0:0.0 + (Itrim[1])?2*i0:0.0 + (Itrim[2])?4*i0:0.0 + (Itrim[3])?4*i0:0.0):0.0;

elaborator generates an error message.

Error: analog event control statements require event arguments

Regards.

Pavel.

Title: Re: detecting discrete events in analog contents
Post by Geoffrey_Coram on Feb 26^th, 2007, 9:35am

You could try the "cross" function:

@(cross(en -vdd/2) or cross(Itrim[0] - vdd/2) or cross(Itrim[1] - vdd/2))

Title: Re: detecting discrete events in analog contents
Post by Ken Kundert on Feb 26^th, 2007, 11:46am

Pavel,
@cross cannot be applied to logic signals. My experience with AMS Designer is that for some reason it does not support "@(en or Itrim)". Instead you should try "@(posedge en or negedge en or posedge Itrim or negedge Itrim)".

-Ken

Title: Re: detecting discrete events in analog contents
Post by Andrew Beckett on Feb 26^th, 2007, 3:12pm

Ken,

That's very surprising. I just tried this:

Code:

module top;

reg fred;
reg harry;

initial begin
fred=1;
harry=1;
end

always #50 fred=~fred;
always #60 harry=~harry;

always @(fred or harry) $strobe($time," ",fred," ",harry);

always #2000 $finish;

endmodule

and it worked perfectly. Admittedly it's a pure digital example, but I'd be rather surprised if it made a difference.

Regards,

Andrew.

Title: Re: detecting discrete events in analog contents
Post by Ken Kundert on Feb 26^th, 2007, 3:33pm

Oh yeah, it works fine in Verilog. Try putting the @ statement in an analog block. That is where I would expect you to experience the problem.

-Ken

Title: Re: detecting discrete events in analog contents
Post by Pavel on Feb 27^th, 2007, 12:18am

Geoffrey, Ken, Andrew,

Thank you for your responses. But situation still isn't clear.

Quote:

You could try the "cross" function:

@(cross(en -vdd/2) or cross(Itrim[0] - vdd/2) or cross(Itrim[1] - vdd/2))

en and Itrim are digital signals, but cross is analog function (applied to analog signals)

Quote:

Instead you should try "@(posedge en or negedge en or posedge Itrim or negedge Itrim)".

Itrim is 4-bit digital bus. Is posedge and negedge work for buses also? Or you mean that one should use posedge or negedge for every bit. But if bus width is 32 or more...

In Verilog-AMS LRM on page 157 (ch. 8.3.4) they give types of event expression that could be used in event detection statement in analog block. Among these types they mention digital expression. What does this term mean. I tought that it's just statement that copmpliant with standard Verilog. In standard Verilog statement @(en or Itrim) is valable.

Regards.

Pavel.

Title: Re: detecting discrete events in analog contents
Post by Geoffrey_Coram on Feb 27^th, 2007, 5:03am

Pavel wrote on Feb 27^th, 2007, 12:18am:

en and Itrim are digital signals, but cross is analog function (applied to analog signals)

Indeed, I missed that point, and Ken pointed that out.

Title: Re: detecting discrete events in analog contents
Post by Andrew Beckett on Feb 28^th, 2007, 6:52am

Ken,

You're quite right (of course). I've even hit this in the past, so my memory is failing me here...

If I do:

Code:

`include "disciplines.vams"

module top;

reg fred;
reg harry;
electrical src;
electrical gnd;
electrical sampled;
ground gnd;
real samp;

vsource #(.type("sine"),.ampl(1.0),.freq(10e6)) v1(src,gnd);

initial begin
fred=1;
harry=1;
end

always #50 fred=~fred;
always #60 harry=~harry;

always @(fred or harry) $strobe("digital: ",$time," ",fred," ",harry);

always #2000 $finish;

analog begin
@(fred or harry) begin
//@(posedge fred or posedge harry or negedge fred or negedge harry) begin
$strobe("analog: ",$abstime," ",fred," ",harry);
samp=V(src);
end

V(sampled)<+transition(samp,1n,1n);
end

endmodule

Then I get an error during elaboration. If I comment out the @(fred or harry) and uncomment the line after, it all works OK.

This is actually mentioned in the Verilog-AMS Reference manual, in the appendix (F) which covers unsupported language features. There's a PCR (351651) asking for this to be implemented.

Regards,

Andrew.

Title: Re: detecting discrete events in analog contents
Post by Pavel on Mar 2^nd, 2007, 3:59am

I found approach how to detect bus activity in analog process.
It's sufficient to create additional clock that senses whole necessary digital activity,
and then employ this clock in analog process.

Code:

electrical i1u_n1, i1u_p1, i2u_n1, i2u_n2, i2u_n3, i2u_n4, i2u_n5, i3u_p1, vbn1, sup;
logic en;
logic [3:0] Itrim;
reg event_clk = 0;

real i_total;
localparam i0 = 1u;
localparam di = 100n;

always @ (en or Itrim) event_clk = ~event_clk;

analog begin

@(posedge event_clk or negedge event_clk)
i_total = (en)?(i0 + (Itrim[0])?di:0.0 + (Itrim[1])?2*di:0.0 + (Itrim[2])?4*di:0.0 - (Itrim[3])?4*di:0.0):0.0;

I(i2u_n1) <+ i_total;
I(i2u_n2) <+ i_total;
I(i2u_n3) <+ i_total;
I(i2u_n4) <+ i_total;
I(i2u_n5) <+ i_total;

I(i1u_n1) <+ i_total/2.0;
I(i1u_p1) <+ - i_total/2.0;
I(i3u_p1) <+ - i_total*1.5;

$bound_step(100n);

end

But simulation results shows something strange (please, see the picture).
1. It seems that i0 isn't taken into account.
2. i_total behavior doesn't correspond to formula in analog process.

I commited some mistake in my code or this is a simulator bug?

Regards,

Pavel.