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Design >> Mixed-Signal Design >> synopsys DC synthesis problem
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Message started by qlmei on Feb 26^th, 2007, 9:16pm

Title: synopsys DC synthesis problem
Post by qlmei on Feb 26^th, 2007, 9:16pm

Hi all,

There is always "assign" statement in my verilog netlist after synthesis. I tried the following command before compile but it doesn't help. Please advise.

set_fix_multiple_port_nets -all -buffer_constants
set_simple_compile_mode true
set hdlin_keep_signal_name none

Title: Re: synopsys DC synthesis problem
Post by ywguo on Feb 26^th, 2007, 11:04pm

Hi, qlmei,

I resolve this problem by define new naming rules before writing netlist out. Just like this :
define_name_rules verilog -remove_internal_net_bus -equal_ports_nets.
Also you need the set_fix_multiple_port_nets –all -buffer_constants .

Yawei

Title: Re: synopsys DC synthesis problem
Post by ywguo on Feb 27^th, 2007, 5:39pm

Hi,

There is another solution.

set verilogout_no_tri ture
set hdlout_internal_busses true
set bus_inference_style "%s\[%d\]"
set_fix_multiple_port_nets -all -buffer_constants

Yawei