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Design Languages >> Verilog-AMS >> processing global vdd! in AMS code
https://designers-guide.org/forum/YaBB.pl?num=1172585361

Message started by Pavel on Feb 27^th, 2007, 6:09am

Title: processing global vdd! in AMS code
Post by Pavel on Feb 27^th, 2007, 6:09am

Hello,

I modelize cells that are already made in Virtuoso Schematic. Some cells include global vdd! signal.
How can I process this signal im my AMS code?

Regards.

Pavel.

Title: Re: processing global vdd! in AMS code
Post by Andrew Beckett on Feb 27^th, 2007, 3:55pm

Pavel,

Globals get netlisted as an out of module reference in schematics - in the cds_globals module. If my memory is correct, it would end up as cds_globals.\gnd! (or something like that). Take a look at the netlist from a schematic containing gnd!, and you'll see the name used. Then you can use the same out of module reference in your verilogams code.

Regards,

Andrew.

Title: Re: processing global vdd! in AMS code
Post by Pavel on Feb 28^th, 2007, 12:57am

Andrew,

Thanks for response. I tried your suggestion (at least as I understood it).
I checked spectre netlist (file input.scs). The name of signal is vdd!.
Then I declared it in my code as

electreical vdd!;

and then used it in my code.

When I tried to compile it parser gives following error message each time when it meets vdd!

ncvlog: *E,EXPSMC ............................................. expecting a semicolon (';')

Regards,

Pavel.

Title: Re: processing global vdd! in AMS code
Post by Andrew Beckett on Feb 28^th, 2007, 7:03am

For a start, you'd need to escape the name because it has an exclamation mark in it - so it would be \vdd! ; (note the space before the semicolon - needed because an escape escapes everything up to the next space).

However, I don't understand why you're looking at a spectre netlist (input.scs) to find the syntax? AMS Designer can include spectre model files, but you're trying to connect (I assume) a global in a schematic netlisted for AMS Designer to the same signal in your Verilog-AMS code? If you're using AMS in ADE, you can look at the resulting schematic netlist. If using the hierarchy editor, you can look at the verilog.ams file in the schematic view in your library. Or you could just look at it in the simvision code browser.

There's no such thing as a global in Verilog, which is why the out of module reference approach is used.

Regards,

Andrew.

Title: Re: processing global vdd! in AMS code
Post by Pavel on Feb 28^th, 2007, 7:28am

Ok, parser passed. :)

Thanks, Andrew