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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> SpectreVerilog Problem https://designers-guide.org/forum/YaBB.pl?num=1172777115 Message started by danda821 on Mar 1st, 2007, 11:25am |
Title: SpectreVerilog Problem Post by danda821 on Mar 1st, 2007, 11:25am I am using SpectreVerilog. If I use functional view for digital blocks, I got x state for all digital signal. If I use spectre model for all blocks (digital and analog), or use spectre model for some digital blocks, the simulation results are right. It seems like the timing is right only after binding some digital blocks to spectre model. I tried timescale of 10p/1p, 100p/1p, no different. Can someone help me on this? thanks. |
Title: Re: SpectreVerilog Problem Post by bernd on Mar 2nd, 2007, 3:13am This may result because of - non proper initialized digital blocks, you may forgot to reset some FF?! - or wrong timing and/or delay options settings for an explanation have a look at the attached pdf. Bernd |
Title: Re: SpectreVerilog Problem Post by danda821 on Mar 2nd, 2007, 7:56am Thanks. I used the global timescale as you mentioned in the pdf file. There are many dff without RS in my circuit, which may cause the problem. Is there anyway to initilize them in spectreverilog? Thank you. bernd wrote on Mar 2nd, 2007, 3:13am:
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