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Design >> Mixed-Signal Design >> Idle pattern of sigma-delta A/D converters
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Message started by ywguo on Mar 4^th, 2007, 3:24am

Title: Idle pattern of sigma-delta A/D converters
Post by ywguo on Mar 4^th, 2007, 3:24am

Hi, Guys,

What is idle pattern? Is it always at half the sampling frequency for one-bit sigma-delta A/D or multi-bit sigma-delta A/D?

Thanks
Yawei

Title: Re: Idle pattern of sigma-delta A/D converters
Post by vivkr on Mar 5^th, 2007, 2:53am

Dear Yawei,

The idle pattern is the response of a modulator to a DC excitation. On average,
it should be at Fs/2 for a modulator with 1-bit quantizer, and also for a multibit
one if I understand correctly because only 2 of the multibit levels are likely to be
used (closest to the midlevel) unless you add randomizing dither to break the tones, which
for a multibit delta-sigma is the standard way to remove idle patterns, and which
does not work well for 1-bit quantizers.

However, the topic is relatively complex. I would recommend that you look at
a book on introductory nonlinear systems. A good visualization is also offered
in the book "Understanding delta sigma converters" by Schreier and Temes in Chapter
2 (See Fig. 2.23).

Regards
Vivek

Title: Re: Idle pattern of sigma-delta A/D converters
Post by ywguo on Mar 7^th, 2007, 6:26pm

Dear Vivek,

Thanks. Somebody recommended that book to me, too. I will try to get that book and read it.

Yawei