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https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> input clock jitter https://designers-guide.org/forum/YaBB.pl?num=1173175301 Message started by sivacharan on Mar 6th, 2007, 2:01am |
Title: input clock jitter Post by sivacharan on Mar 6th, 2007, 2:01am Hi all, My Q is regarding how can we specify input clock jitter in cadence? Assume that i am using vpulse from analogLib as a clock. I am unable to figure out where i can give the input clock jitter?? Thanks. |
Title: Re: input clock jitter Post by Ken Kundert on Mar 6th, 2007, 9:48am The built-in sources do not implement jitter. You will need to use Verilog-A instead. Look on verilog-ams.com to find fixed-frequency oscillators (with and without jitter). -Ken |
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