The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> CP noise for CDR PLL https://designers-guide.org/forum/YaBB.pl?num=1173200826 Message started by Visjnoe on Mar 6th, 2007, 9:07am

Title: CP noise for CDR PLL Post by Visjnoe on Mar 6th, 2007, 9:07am Dear all, I know that for a clock generation PLL the CP noise contribution towards to the output is scaled by the ratio of the on-time of the PFD and the reference period. For a CDR (Clock and Data Recovery) PLL however, in the locked state both UP/DOWN pulses are high for half the clock period. Can it therefore (as I assume) be concluded that the CP noise contribution is much higher (given the same current value) for a CP in a CDR PLL than in a clock generation PLL? Consequently, is it true that the CP current should be typically much larger for a CDR PLL (for the same jitter)? Regards Peter

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