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Design >> High-Speed I/O Design >> IO CLK/CLKB Buffer SSTL_18 Compliance
https://designers-guide.org/forum/YaBB.pl?num=1173532176

Message started by Anguraj.K on Mar 10^th, 2007, 5:09am

Title: IO CLK/CLKB Buffer SSTL_18 Compliance
Post by Anguraj.K on Mar 10^th, 2007, 5:09am

Hi Experts,

I'm a new born baby to this Elite Community!
Greeting to all of You!

I need your help in the below question! I believe this would be a best place for me to get an answer
When I design a SSTL_18 compliant IO buffer for differential signals,
JEDEC spec (JESD815) : Differential Signals (CLK/CLKB)cross points need to be in the range power/2 +- 0.125V.
This is for a test condition :
clk buffer --> r 20ohm --> tline (50ohm)---- -->
|
---->across a 100ohm resistor ----> receiver
|
clkbar buffer --> r 20ohm --> tline (50ohm) ---->

Here I believe depending on the receiver i/p load , the cross point is going to vary.

So To test this scenario, how are you people handling without a solid receiver load (this varies from customer to customer who uses this IO pad)

Sorry for being too specific in my question.

Can anyone throw me some lights on their experience to this scenario?

Title: Re: IO CLK/CLKB Buffer SSTL_18 Compliance
Post by ywguo on Mar 20^th, 2007, 2:52am

Hi, Anguraj,

I think that a specific question is better, because we can discuss it with less misunderstanding and mistakes.

About your question, sure that the load is important in the simulation and field test. Normally the load should be defined in the related standard, that is JESD 815 in your case. Furthermore, I think the loading at the plus and minus inputs are almost the same in first order. They don't affect the cross points obviously.

Best regards,
Yawei