The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Saturating amplifier following VCO
https://designers-guide.org/forum/YaBB.pl?num=1173576002

Message started by Amit Singh on Mar 10^th, 2007, 5:20pm

Title: Saturating amplifier following VCO
Post by Amit Singh on Mar 10^th, 2007, 5:20pm

Hi,
I am currently designing a CDR circuit. After the VCO, do i am trying to have a saturating amplifier to make the edges of the clock signal sharp.
I am finding it difficult to get sharp slope in my 180nm technology with clock signal at 6.5G.
Can you please highlight any disadvantge if i directly use sine wave output of VCO as clock in my CDR circuit.

Regards,
Amit