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Design Languages >> Verilog-AMS >> basics for verilog-A and vhdl-ams ?
https://designers-guide.org/forum/YaBB.pl?num=1173601378

Message started by richard88 on Mar 11^th, 2007, 12:22am

Title: basics for verilog-A and vhdl-ams ?
Post by richard88 on Mar 11^th, 2007, 12:22am

Hi,
Could anyone point me to a link for basic material on verilog-A and vhdl-ams pertaining to analog circuit modelling ? What are the pros and cons of using either of them and if there is a chance one of them going to be obsolete soon ?

Thanks, :)
Richard

Title: Re: basics for verilog-A and vhdl-ams ?
Post by Geoffrey_Coram on Mar 13^th, 2007, 7:38am

If you're doing analog modeling only, you should probably use Verilog-A, since it's supported by the major analog simulators (HSpice, Spectre, Eldo). I found it was fairly easy to learn Verilog-A by example -- look at the models on this site or elsewhere on the web. But grab a copy of the LRM as a reference.