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Design Languages >> Verilog-AMS >> Frequency lock in CDR
https://designers-guide.org/forum/YaBB.pl?num=1173613747

Message started by Amit Singh on Mar 11^th, 2007, 4:49am

Title: Frequency lock in CDR
Post by Amit Singh on Mar 11^th, 2007, 4:49am

Hi,
I am simulating a Alexender bang-bang CDR at circuit level. I am using just the phase detector in my design and ther is no frequency detector.
In my closed loop simulation except the VCO all blocks are at the circuit level and i'm verilog model of VCO.
I have seeing in my simulation that the control voltage is not settling to correct value, in terms of frequency my clock freq should get stable at 6.25G but it is getting stable at 6.6G. What can be the reason for this ? Do i need to have explicit frequency detector ?

regards,