The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> how simulate veriloga model in DC
https://designers-guide.org/forum/YaBB.pl?num=1173952870

Message started by Pavel on Mar 15^th, 2007, 3:01am

Title: how simulate veriloga model in DC
Post by Pavel on Mar 15^th, 2007, 3:01am

Hello

I didn't find in documentation how can I simulate veriloga/verilogams models in DC.
I tried following approach:
1. created veriloga model
2. created symbol for it
3. created schematic testbench - dc stimuli + model
4. invoked ADE
5. in ADE changed simulator for ams
6. choose dc analysis in ADE

But there are no any parameter to specify - no source to sweep, start/stop/step, etc.. (please, see the picture)

Regards,

Pavel.

Title: Re: how simulate veriloga model in DC
Post by Andrew Beckett on Mar 15^th, 2007, 6:39am

AMS Designer does not support (currently) doing a DC sweep. Bear in mind that the digital part would need some time to react to a changing parameter or voltage, so it doesn't make so much sense to do a DC sweep with a mixed-signal simulator as it does with a pure analog simulator (where you can calculate the DC by removing the capacitors and shorting the inductors).

So the only choice you have is to do the DC operating point.

Regards,

Andrew.