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Design Languages >> Verilog-AMS >> Adding phase noise in the VCO model
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Message started by Amit Singh on Mar 15^th, 2007, 7:08am

Title: Adding phase noise in the VCO model
Post by Amit Singh on Mar 15^th, 2007, 7:08am

Hi,
I am simulating a PLL and using verilog model of VCO. How can i include phase noise of VCO in to this model ?

Thanks for your help,

Amit

Title: Re: Adding phase noise in the VCO model
Post by Ken Kundert on Mar 15^th, 2007, 1:27pm

I suggest you read "Predicting the phase noise and jitter of PLL-based frequency synthesizers", which can be found on www.designers-guide.org/Analysis.

-Ken