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Design >> Analog Design >> Lag-Lead Filter Design
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Message started by elec_eng on Mar 16^th, 2007, 6:59am

Title: Lag-Lead Filter Design
Post by elec_eng on Mar 16^th, 2007, 6:59am

Hi.

I need to use a lag-lead filter. The configuration of this filter can be seen on the attachment.

It will be used on a PLL cirucit with chip LM565. The data sheet can be found at: http://www.national.com/ds/LM/LM565.pdf

I need to work out the values for C1, C2 and R2 if the cut off frequency is 1kHz.

What equations can i use?

OR

What would the values for C1, C2 and R2 need to be?

Please help. Thanks.