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Design >> High-Speed I/O Design >> CDR Clock
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Message started by Amit Singh on Mar 19^th, 2007, 12:05am

Title: CDR Clock
Post by Amit Singh on Mar 19^th, 2007, 12:05am

Hi,
I am working a Clock data recovery circuit at 6.5G in 0.18um tech. Do i need to saturate the clock after the VCO, or is it ok to feed the sine clock to the phase detector.

Thanks for the help,

Title: Re: CDR Clock
Post by SATurn on Mar 21^st, 2007, 10:28am

Hello,

It depends on your PD topology. If it is based on SCL (source-coupled logic) topology, then it should be fine. Else, you are using CMOS gates in your PD, you should convert the levels to CMOS level.

SATurn