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Design >> Analog Design >> Threshold Voltage
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Message started by avlsi on Mar 21^st, 2007, 1:29am

Title: Threshold Voltage
Post by avlsi on Mar 21^st, 2007, 1:29am

Hi all,

As we increase the channel length, why is that the threshold voltage decreases? What is the reason behind this?

Thanks in advance.

Title: Re: Threshold Voltage
Post by Michiel on Mar 22^nd, 2007, 4:25pm

avlsi wrote on Mar 21^st, 2007, 1:29am:

Hi all,

As we increase the channel length, why is that the threshold voltage decreases? What is the reason behind this?

Thanks in advance.

There are many factors that influence the threshold voltage. Some basic ones are described in books like "Design of Analog CMOS Integrated Circuits". http://www.designers-guide.org/Books/

Personally I don't even want to know all the physics behind it.

There is only one reliable way to make sure that two transistors have about the same (nominal) threshold voltage. Use identical parameters and layout.

Title: Re: Threshold Voltage
Post by krishnap on Mar 23^rd, 2007, 3:02am

Because of short channel effects VT decreases as channel length decreases.
Exception to this is Reverse short channel effect, where VT increases as channel length reduces.

Best regards,
Krishna

Title: Re: Threshold Voltage
Post by mg777 on Mar 23^rd, 2007, 8:09am

As L decreases the drain and source depletion regions steal more of the gate's field lines, so the V_TH actually decreases while the subthreshold conduction increases. OTOH if tox decreases faster than L, then you put the gate back in control (C_ox increases) leading to a better trade-off between V_TH and subthreshold slope.

M.G.Rajan
www.eecalc.com

Title: Re: Threshold Voltage
Post by mc66 on Mar 29^th, 2007, 7:11am

there have roll off curve for vt

eg: when L is between 0.13 ~ 0.4(just estimated, 130mn technology) , vt is decrease with L decrease (SCE effect)

but when L is between 0.4um and above , vt is incresae with L decrease (RSCE effect , halo implant cause this)

Title: Re: Threshold Voltage
Post by SATurn on Mar 29^th, 2007, 12:27pm

By reducing the device length, the field created by drain (or source) can bend the fermi level inside the substrate and attract some minority carriers. There is a very good discussion on this issue in Taur's book.

SATurn