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Design >> RF Design >> Real clock coupling?
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Message started by cyun on Mar 22^nd, 2007, 12:28am

Title: Real clock coupling?
Post by cyun on Mar 22^nd, 2007, 12:28am

Dear all,
I found a very strange problem in TRAN simulation.
My test bench includes a port for input, pure rf/analog circuits, digital circuits, and a clock for the digital circuit (realized by an ideal vpulse voltage source).
After simulation, I found the clock appears at the output spectrum.
Then I remove the digital circuit. Now only a port, rf/analog circuits, and a floating clock in the test bench (negative port of clock is connected to ideal gnd).
The clock still appears with almost the same maganitude.
It's very strange! The clock doesn't connection to any node, just co-simulation with other circuits. How can it couple to output?
I use "spectre" to simulate and the accuracy is set to "liberal" .
The clock maganitude will reduce if the accuracy set to "conservative", but still appear.

It seems the coupling from software calculation. Am I right?
If yes, how to reduce the effect in "liberal" simulation?

Title: Re: Real clock coupling?
Post by mg777 on Mar 26^th, 2007, 10:25am

Check if the clock is sneaking in via a behavioral model on the analog side - maybe an ADC.

Also make sure the clock strength you're seeing is at a reasonable level, e.g; greater than -80 dBc. For example inverting an ill conditioned matrix can cause 'numerical noise'. As a guide, 32 bit accuracy is -192 dB.

M.G.Rajan
www.eecalc.com