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Design Languages >> Verilog-AMS >> decimation filter CIC, two's complement
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Message started by trond on Mar 22^nd, 2007, 5:40am

Title: decimation filter CIC, two's complement
Post by trond on Mar 22^nd, 2007, 5:40am

Hello,

I wanted to implement a quick 2 second order CIC decimation filter based on the cascade of two accumulators, followed by a rate reduction by M, followed by two differentiators. The input to the decimator is the one bit output of a Sigma Delta modulator, i.e. 0,1,1,0,0,0,1......

This is was i am using:

\\INTEGRATORS
@(cross(V(clk) -0.5 , 1)) begin //Fast clk
accum1=accum1+sd_output;
accum2=accum2+accum1;
end

\\RE-SAMPLE
@(cross(V(clkM) -0.5 , 1)) begin //Decimated clk
x1=accum2;

\\DIFFERENTIATORS
d1=x1 - absdelay(x1, 4/Fs);
d2=d1 - absdelay(d1, 4/Fs);

Then I read out d2 and save to a file for processing in Matlab.

Now, this works fine BUT, the integrator registers will get quite large. So i wanted to use modulo arithmetic by using:

\\INTEGRATORS
@(cross(V(clk) -0.5 , 1)) begin //Fast clk
accum1=(accum1+sd_output) % 1024;
accum2=(accum2+accum1) % 1024;
end

But there must be something wrong as the final output does not contain my signal anymore. How does one do two's complement or modulo N arithmetic in VerligA\MS???/

thanks for any tips.

Title: Re: decimation filter CIC, two's complement
Post by trond on Mar 22^nd, 2007, 7:01am

I just realized that the % operator is more like the remainder, rather than the modulo operator I am used to from Matlab. So,
mod(-3,8) = 5 BUT -3%8 = -3.
I was browsing the VerilogA LRM but could only find the % operator. Is there another command i can use to obtain the desired results/

Cheers

Title: Re: decimation filter CIC, two's complement
Post by Andrew Beckett on Apr 12^th, 2007, 1:27am

You can use the following function:

Code:

analog function real mod;
input num,den;
real num,den;

mod = num<0 ? num%den+den : num%den;
endfunction

Regards,

Andrew.

Title: Re: decimation filter CIC, two's complement
Post by trond on May 3^rd, 2007, 12:26am

Cheers Andrew. All fine now :)