The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Current cell mismatch in DAC
https://designers-guide.org/forum/YaBB.pl?num=1175059623

Message started by ywguo on Mar 27^th, 2007, 10:27pm

Title: Current cell mismatch in DAC
Post by ywguo on Mar 27^th, 2007, 10:27pm

Hi, Guys,

As well known, the mismatch of current sources determines the linearity of DAC. Here I am confused by the coefficient in the current mismatch formula.

In Geert A. M. Van der Plas, "A 14-bit Intrisic Accuracy Q² Random Walk CMOS DAC," the formula is (1) in the following attachment. In Marcel J. M. Pelgrom, et. al, “Matching Properties of MOS Transistors,” the formula is (2) in the following attachment. The former has a coefficient 1/2, while the latter has a coefficient 1.

Which one is correct?

Thanks
Yawei

Title: Re: Current cell mismatch in DAC
Post by ywguo on May 10^th, 2007, 8:29am

Any comments are appreciated. :(

Title: Re: Current cell mismatch in DAC
Post by RobG on May 10^th, 2007, 9:00am

They are both correct, but they are for different things. Pelgrom's formula (2) is for the mismatch between a pair of devices.... but pairs don't make sense in a dac -- you have to consider each contribution individually. To get around this (1) normalizes the mismatch contribution to a single device. That way you can calculate the mismatch contribution of each device and add them up.

Note that if you take the contributions of two devices using (1), you get (2).

Bottom line is that you want to use (1).

rg

Title: Re: Current cell mismatch in DAC
Post by raduga on May 16^th, 2007, 5:27am

Hi,

The 1/2 factor comes in the first equation because if you check the pelgrom's paper
it is for the mismatch of a parameter in 4 devices instead of two. I guess the 14 bit
random walk paper implements a current cell as a combination of 4 unit current
cells. Therefore the factor of 1/2 comes into picture.

If you have any other question regarding this please feel free to mail me at

mangesh [at] aol [dot] in

Raduga ..

Title: Re: Current cell mismatch in DAC
Post by ywguo on May 16^th, 2007, 6:35pm

Hi, Robert and Raduga,

Thank you very much.

Raduga, I read the Pelgrom's paper again. The equation is for the mismatch of a pair of MOS devices there. So I agree with Robert.

Yawei

Title: Re: Current cell mismatch in DAC
Post by raduga on May 16^th, 2007, 10:47pm

Hi ywguo,

I think, you should check the equation #6 in the Pelgrom's paper. It is given for the four
crosscoupled transistors and therefore there is a factor of (1/2) included than for the
equation #5, which is there on the second page of the paper.

Regards
Raduga

Title: Re: Current cell mismatch in DAC
Post by ywguo on May 17^th, 2007, 8:51pm

Hi, Raduga,

I think that equation (6) in Pelgrom's paper is for a pair of devices composed of 4 cross-coupled idential MOS transisotr with demension ration W/L. That means area of each device is 2×WL . Because 4 cross-coupled MOS are not placed in one row, equation (6) is a little different from equation (5). The random variation is affected by both x and y directions in equation (6) while only by x direction in equation (5).

Best regards,
Yawei

Title: Re: Current cell mismatch in DAC
Post by driveforce on May 25^th, 2007, 12:26am

These equations are kind of conservative, Monte carlo simulations shows better result.

Title: Re: Current cell mismatch in DAC
Post by ywguo on May 25^th, 2007, 1:04am

Hi,

RobertZ wrote on May 25^th, 2007, 12:26am:

These equations are kind of conservative, Monte carlo simulations shows better result.

Would you please introduce how you set up the simulation? Do you simulate with 2 MOS transistors? Does your model for MOS transistor have mismatch parameter? Where do you get the constants Avt, Abeta from?

Thanks
Yawei

Title: Re: Current cell mismatch in DAC
Post by raduga on Jun 20^th, 2007, 1:57am

Hi Yawei,

I really don't know about the monte carlo simulation; but the
Abeta and Avt prameters you can find in the standard pdk
docs of most of the reputed foundries like UMC and TSMC.

Thanks and Regards

Raduga