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Design >> Mixed-Signal Design >> 14bit pipeline adc post-simulation problem
https://designers-guide.org/forum/YaBB.pl?num=1175365813

Message started by ponderboy on Mar 31^st, 2007, 11:30am

Title: 14bit pipeline adc post-simulation problem
Post by ponderboy on Mar 31^st, 2007, 11:30am

I'm designing a 14-bit pipeline ADC,it has a 4-bit first stage,using 16 comparators and a 105dB,2GHz BW two stage amplfier for MDAC,the sampling switch of the first stage MDAC is a bootstraped switch.after layout,I use assura to do RCX extraction.When using decoupled extract option,the post-simulation ouput from a ideal 14bit DAC got a 92dBc SFDR when woring at 85MHz.But when using coupled option to do parasitic capacitor extration,the SFDR drops to 81dBc at same sampling frequency and same input analog signal. I guess the lost of 11dBc may due to parasitic capaciotr coupled between sampling capacior of MDAC,or from the nonlinearity of switch.what should i do?