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Design >> Analog Design >> Charge Pump Design Issue
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Message started by narcissus on Apr 3^rd, 2007, 9:21pm

Title: Charge Pump Design Issue
Post by narcissus on Apr 3^rd, 2007, 9:21pm

Hi expert ,

I had design a PFD(phase frequency detector) and Charge Pump(CP). PFD is conventional structure of three state PFD. The Charge Pump is also conventional structure which include a dummy current branch and actual current branch with unit gain buffer in order to reduce switch noise. Charge and discharege current is 100uA.

When simulation of PFD+CP , and load with 10pF Cap(CP's output port connect 10pF Cap to Ground), the function is right, even added with bond wire model(two cap and one inductor).

But ,we taped out the chip. During test the chip (PFD+CP) with 10pF Cap, the function(charge and discharge) is not right.(output DC level is not change with frequency difference change), CP's output only show some irregular sine waveform ,and amplitude is about 20-100 mV. DC level is fixed.

If excepted the bias problem for CP, do you advice any other problem for this result?

any suggestion, thanks a lot
:)

Title: Re: Charge Pump Design Issue
Post by Visjnoe on Apr 4^th, 2007, 2:08am

Dear narcissus,

since you mention the inclusion of a bondpad model in your PFD/CP simulation, can I conclude that you have an external LF?

The 10pF cap you mention, is this the largest capacitor in a classic second-order LF? If not, what are the values of your external LF components?

If your LF is external, I would look at the external LF GND versus the on-chip PLL GND...any difference here might kill you.

Further more, have you made sure (by simulation) that your PFD digital output creates a valid logic HIGH/LOW level that is able to steer the CP switches?

Let's first answer these questions and take it from there.

Regards

Peter

Title: Re: Charge Pump Design Issue
Post by narcissus on Apr 4^th, 2007, 8:23pm

Dear Visjnoe,

Thanks for your reply.
yes, i using the second-order LF for whole PLL. those value is Cp=82pF, Rz=3.32K,Cz=4.7nF. those value determind by loop BW and Phase Margin by AC analysis.

During the simualtion PFD+CP ,I using the LF or one individual 10pF Cap , function is same, just the amplitude of noise is not same Due to LF have strong filter effort.

But when I test the PFD+CP, I just using one 10pF Cap for simplicity. I guess the chip's function is Ok, but test result is so bad.

1. For the GND , it is no problem , it should be connect together with PLL's GND
2. For the CP swithes, I using the transmmison gate as switch(size is smaller,W/L=2/0.18), also the PFD ouput digital signal have strong driver capacity.(the rise time is about 60ps under pre-layout simulation).

Due to the DC Current is so large(20 times) than simulation result without input signal. So now I only doubt the bias circuit have problem.

do have any advice for how to test PFD or charge pump ? so I try that on next phase. Thanks a lot.

Title: Re: Charge Pump Design Issue
Post by ywguo on Apr 5^th, 2007, 2:39am

Hi, Narcissus,

Did you put the PFD+CP in a feedback loop like a PLL when you tested? 10pF cap is not sufficient to make the PLL stable.

Best regards,
Yawei

Title: Re: Charge Pump Design Issue
Post by narcissus on Apr 8^th, 2007, 6:52pm

Hi, Yawei,

I just test PFD+CP in open loop . But in my whole PLL design , the Cap value should be 82pF for stable.

Best Regards,

Title: Re: Charge Pump Design Issue
Post by ywguo on Apr 9^th, 2007, 12:18am

Hi, Narcissus,

How much volt is the DC output level? I suggest that you test the PFD+CP in a PLL.

Thanks
Yawei