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Design >> Analog Design >> NMOS body layout connection in nwell process
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Message started by webb0111 on Apr 16^th, 2007, 5:23pm

Title: NMOS body layout connection in nwell process
Post by webb0111 on Apr 16^th, 2007, 5:23pm

Hello,

I am having a problem in tsmc025rf technology layout in Cadence. In my schematic design there are 4-terminal transistors. So in my analog designs, I used body-source connections for all transistors, unlike in digital design where the body is connected to either VDD or VSS. I have been unable to determine a way to do NMOS body-source connections in layout because it is an nwell process and thus all NMOS share a p-substrate. In PMOS this can be done by isolating the nwell for different transistors (I think).

This leads me to believe that somehow I need to isolate the p-substrates for each NMOS that does not have its source directly connected to VSS, and then connect the isolated substrates to the respective sources. The Art of Analog Layout was a small help, but I do not understand how to apply its technique.

Any help on this topic is appreciated. If more information is needed I will be happy to oblige.

Thanks again,

Matt

Title: Re: NMOS body layout connection in nwell process
Post by ywguo on Apr 16^th, 2007, 7:40pm

Hi, Matt,

If you use said twin-well process, all NMOS transistors are placed in a common pwell. I mean what you called p substrate. If you want to tie the body of all NMOS transistors to their sources, a triple-well process are required. P-well are isolated by deep-nwell over there and are not required to be tied to vss.

Regards,
Yawei

Title: Re: NMOS body layout connection in nwell process
Post by Croaker on Apr 16^th, 2007, 8:35pm

Matt, in brief, you're stuck for NMOS unless the process also has p-wells. Check the design rule manual.

If you don't have p-wells, all NMOS bodies are the same, and so you should tie them to VSS. The problem is that you get a body effect because Vsb is not zero, and the threshold voltage is higher. If the source and body in a well are shorted, you add a source cap resulting from the junction of the n-well and p-substrate. There's no free lunch.

Title: Re: NMOS body layout connection in nwell process
Post by skas20 on Apr 17^th, 2007, 2:14am

Matt,

For P-MOS, if it require a seperate body source connection, then seperating the N-well will do the job.
For N-MOS, if you want to isolate the device from the common substrate that is p- , you need to use a seperate layer called DNELL(Deep Nwell). This will be completely covered with Nwell layer as a ring anound it always. Now this DNELL substrate can be considered as another p- substrate and you have to connect to the desired potentioal using substrate contacts.

One important thing to be noted is that this layer is an extra MASK layer. and certainly cost assoiated with it.

Regards.
sk.

Title: Re: NMOS body layout connection in nwell process
Post by Rocky.Lee on Apr 17^th, 2007, 7:47am

matt,

as YWGUO and SKAS20 said, Deep Nwell will isolate you NMOS transistors and then you can tie S and B of your NMOS together. I remember that TSMC25RF support the DNWELL by add a mask, as SKAS20 mentioned. furthermore,use DNwell NMOS transistors will make your layout area much larger than normal NMOS.

rocky

Title: Re: NMOS body layout connection in nwell process
Post by webb0111 on Apr 17^th, 2007, 8:39am

Thank you all for your help. So now I have added the layers DNELL and PWELL, and I believe I have isolated the nmos. Now my problem is how to connect the body and source of the isolated nmos. I have M1_NWELL contacts, but no M1_PWELL contacts. When using the M1_PSUB contact, during extraction I get the error of having/causing multiple stamped connections, because it is actually connecting to the entire substrate.

Again thank you.

Matt

Title: Re: NMOS body layout connection in nwell process
Post by webb0111 on Apr 17^th, 2007, 9:05am

It seems that using the PSUB2 layer instead of the PWELL layer works. Thanks everyone.

Title: Re: NMOS body layout connection in nwell process
Post by ywguo on Apr 17^th, 2007, 8:42pm

Hi, Matt,

You'd better look into the foundry manuals to find the exact definition of PSUB2 layer. It is not bad to be cautious.

Best regards,
Yawei

Title: Re: NMOS body layout connection in nwell process
Post by krishnap on Apr 17^th, 2007, 11:21pm

usually PSUB2 layer is the pseudo layer which differentiates between two p-substrates.
e.g., if one part of the substrate is AGND1 and other part is AGND2, then drawing pusb2 layer in AGND2
isolates that from AGND1.
In this case AGND1 is usual substrate and AGND2 area is isolated one.

Title: Re: NMOS body layout connection in nwell process
Post by ywguo on Apr 18^th, 2007, 12:43am

Hi, Krishnap,

Do you mean AGND2 is isolated from AGND1 by a deep nwell? I think that maybe they are just isolated mutually in LVS check.

Thanks
Yawei

Title: Re: NMOS body layout connection in nwell process
Post by vivkr on Apr 18^th, 2007, 2:09am

Hi Matt,

I would first try to get hold of a process manual where they show you a cross section of the chip with different wells and the substrate.
Here, you will be able to really see whether or not it is possible to fabricate an isolated pwell at all. Generally, you need a DNWELL for
this. If not, then your design will not work when fabricated.

Generally, it is not possible to tie the bulk of NMOS devices to anything except substrate, and since this is a TSMC process, I am not
sure if you can do it otherwise, but in any case, please check the process manual.

Also, be careful to ensure that the well parasitics are modelled if you are using a source-bulk connection and not tying it to substrate.
Otherwise, your circuit will suffer from performance issues.

Regards
Vivek

Title: Re: NMOS body layout connection in nwell process
Post by krishnap on Apr 18^th, 2007, 10:35pm

Hi Yawei,

In the above mentioned case deep nwell layer is not available to isolate the substrates.
As you pointed out, the psuedo PSUB2 layer will be isolating for the LVS check.
But all the PSUB2 will be surrounded by n-well guardring so that there is
some degree of isolation.

Regards,
Krishna

Title: Re: NMOS body layout connection in nwell process
Post by ywguo on Apr 19^th, 2007, 2:41am

Hi, Krishnap,

Sure the n-well guardring has some extent of isolation. We usually separate multiple ground in one chip using n-well guardring. But the NMOS body is still tied to ground, not source of itself. Matt's problem is to tie NMOS body to its source.

Best regards,
Yawei

Title: Re: NMOS body layout connection in nwell process
Post by krishnap on Apr 19^th, 2007, 3:24am

Thanks Yawei ..
I got the problem regarding the bulk connection.

Regards,
Krishna

Title: Re: NMOS body layout connection in nwell process
Post by LL on Apr 20^th, 2007, 11:58pm

Hello Matt,
I'm going to repeat some info here that have already been posted but I hope I won't do too much of that. My experience is with TSMC .18um and 0.13 RF but I think the 0.25um is not going to be too far (if at all) from those.

To answer you questions:

(1) Yes, a triple well process is needed in order to have NMOS bulk-to-source ties. The Deep Nwell (DNW) option at TSMC will provide the 3rd well for your needs. Notice that I wrote option because this indeed will add additional mask cost (1 mask in this case). But in general most RF designs I've seen take advantage of the DNW option for noise isolation. Plus, if you use TSMC's RF devices, you will have little choice but to use the DNW unless you plan to develop your own model. On the subject of modeling, I've heard from my colleague that previously NMOS in deep well had a different characteristic vs the NMOS outside of deep nwell. However, that's not the case now ... at least it's not in the .18um and .13um processes. TSMC releases the same model deck for both devices.

(2) In regard to your question about LVS, the use of nwell ring and PSUB2 will break the substrate soft-tie and allow you to tie bulk to source for NMOS. Independent of DNW usage, you can get LVS to pass with these "tricks". Notice that I wrote tricks because they are indeed tricks to pass LVS. PSUB2 is not a mask and nwell ring doesn't create a separate well for you. Be very cautious when you use these. Now, getting back to your deep nwell layout, if the layout is done correctly, there should be an nwell ring going around the edge of your DNW layer. The nwell ring will break the substrate for you in LVS and you should not have to use PSUB2. Connection from that point is simple. Psub inside the ring should be tied to the source of that device. On a side note, this design style will create a very large layout. One last comment on LVS, if the .25um LVS deck is anything like the .18u/.13um deck, NMOS inside DNW vs NMOS outside DNW will get extracted with different model names. You schematic have to reflect this to get LVS passed cleanly.

I hope I have answered your questions.

cheers,
LL

Title: Re: NMOS body layout connection in nwell process
Post by webb0111 on Apr 23^rd, 2007, 9:22am

Hello again,

LL, i was wondering if you could clarify about your posting.

Am I to use a dnwell layer surrounded by an nwell ring, as in I only need those two layers to isolate my NMOS (no psub/pwell)?

And for the use of PSUB2 as a trick to pass LVS, my extracted circuit (with use of PSUB2) has very similar characteristics as my schematic circuit, but is this not a true repesentation? I guess my question here is, will it be able to be fabricated or not?

Thanks

matt

Title: Re: NMOS body layout connection in nwell process
Post by LL on Apr 23^rd, 2007, 11:55pm

Hi Matt,
I want to reiterate that my experience have been with .18/.13RF processes and the .25RF should not be that much different. However, I highly recommend you go through at least these 2 docs carefully: (1) mixed signal layout design rules (2) gdsII layer usage. Both should be available off TSMC website and you (or someone in your organization) should have access to it. The design rules manual has the layout rules for dnwell. The gdsII layer usage lists out tapeout layers vs DRC/LVS purpose layers.

To answer your question:

webb0111 wrote on Apr 23^rd, 2007, 9:22am:

Am I to use a dnwell layer surrounded by an nwell ring, as in I only need those two layers to isolate my NMOS (no psub/pwell)?

To achieve what you are trying to do which NMOS bulk to source connection, you need to use the DNWELL layer ... no other way around it. To do so, you need to follow the layout design rules of the DNWELL. If you follow that correctly, PSUB2 and PWELL will not be needed.

webb0111 wrote on Apr 23^rd, 2007, 9:22am:

And for the use of PSUB2 as a trick to pass LVS, my extracted circuit (with use of PSUB2) has very similar characteristics as my schematic circuit, but is this not a true repesentation? I guess my question here is, will it be able to be fabricated or not?

The use of PSUB2 comes in handy in situation where there are multi-grounds in the design for noise isolation (eg. digital gnd vs analog ground). The grounds are routed out separately to IO pads but they may be tied off chip. Potentially, they are the same and PSUB2 provides a way to pass LVS. PSUB2 is not a tape-out layer so it will not be used to fabricate your chip. Covering an area with PSUB2 creates an artificial well for LVS but not a real well on silicon. Yes, your extracted circuit will behave the same since your extract command file is no different from LVS command file.

Hope this helps,
LL

Title: Re: NMOS body layout connection in nwell process
Post by webb0111 on Apr 24^th, 2007, 8:11am

yes thank you for the clarification

matt