The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> error when adding 2 variables https://designers-guide.org/forum/YaBB.pl?num=1176794986 Message started by Pavel on Apr 17th, 2007, 12:29am |
Title: error when adding 2 variables Post by Pavel on Apr 17th, 2007, 12:29am Hello, When modelizing fully differential OTA I've met strange error from veriloga parser. Here are 2 variables that modelize output small-signal behavior Code:
and here is common mode processing Code:
Then I add common-mode part with small signal part to form outputs: Code:
When I compile this code, following error appears: Error: dynamic quantities must be directly accessible to the outputs. What does this error mean? Regards Pavel. |
Title: Re: error when adding 2 variables Post by Pavel on Apr 17th, 2007, 12:40am Sorry, the error message concerns portion of code that follows: Code:
Regards Pavel |
Title: Re: error when adding 2 variables Post by Pavel on Apr 17th, 2007, 1:04am Resolved - for slew rate processing I employed slew function. Regards Pavel |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |