Post by senyou78 on Apr 20th, 2007, 12:43am
hi,
I am trying to simulate Discrete time 1st order delta_sigma Modulator using switch-capacitor(circuit from the book of RICHARD SCHREIER<Understanding Delta-Sigma Data Converter>),
I used this switch code(verilog-A):
include "constants.vams"
`include "disciplines.vams"
module swir(pc,nc,p,c);
input pc , nc;
inout p, c ;
electrical pc,nc,p,c;
branch (p, c) zei , zev;
parameter real vth =0.6;
parameter real dir = +1 from [-1:1] exclude 0;
analog begin
@(cross(V(pc,nc)-vth, dir)); // for timestep control
if(V(pc,nc) > vth)
V(zev) <+ 0;
else
I(zei) <+ 0;
end
endmodule
the schematic of my design is below
and when I simulate the circuit I get this error:
only one connection to nde`I124.net014''
Fatal error found by spectre during topology check.
the following branches form a loop of rigrid branches(shorts) when added to
th e circuit:
V5:p (from net 0156 to 0)
V4:p (from net 0156 to Vref-)
V0:p (from U+ to net 0107)
I186:zerov_flow (from Vref- to net87)
I188:zerov_flow (from net0123 to net0151)
I189:zerov_flow (from net0123 tonet0167)
I connect the control of the switch one pin to the ground and the oder to phi (Vpulse voltage)!
I wanted also to simulate just one switch connected to the capacitor ,I had also an error--> branches form a loop of rigrid branches(shorts)when added the circuit:
V0:p (from _net0 to 0)
so I dont know how to solve this problem ?--> switch connected to the capacitor
can somebody help me to solve this problem?
thanks
best regards
senyou78