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Measurements >> Phase Noise and Jitter Measurements >> CML Modular Programmable Divider Phase noise sim
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Message started by Lance on Apr 20^th, 2007, 6:54am

Title: CML Modular Programmable Divider Phase noise sim
Post by Lance on Apr 20^th, 2007, 6:54am

Anyone know how to simulate the phase noise of a modular programmable divider found in the paper " A family of Low-Power Truly Modular Programmable Dividers in Standard 0.35um CMOS Technology" IEEE JSSC vol.35 no7 July 2000 using Ken's strobe method?

The divider is a ripple counter made up of modulus 2/3 sections in cascade. It effectively combines the prescaler and programmable divider into one cml stage and the cml-cmos conversion now can take place near the comparison frequency. Unlike a normal ripple counter there is a moduls control signal fed back from the last low freq 2/3 stage back upstream stage by stage to the high freq 2/3 stage. The modulus signal instructs when each 2/3 section when to toggle and is the same frequency at each interface so any of them can be used as the low frequency output to the PFD. Each 2/3 section can have half the current of its upstream neighbour. Tapping off the modulus control signal at the first 2/3 stage gives a narrow pulse too fast to operate the cml-cmos converter in reasonalbe current budget. Tapping off the modulus control further down stream gives same frequency but more even duty cycle and longer setup time but then the output would have accumulated jitter! Measuring the jitter of each 2/3 stage individully and summing to get an overall phase noise using Ken's method is a bit more tricky with this beast than a simple ripple counter. Has anyone done this before?