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Design >> Analog Design >> Tail current source sizing MI/SI vs. WI ???
https://designers-guide.org/forum/YaBB.pl?num=1177175093

Message started by eng on Apr 21^st, 2007, 10:04am

Title: Tail current source sizing MI/SI vs. WI ???
Post by eng on Apr 21^st, 2007, 10:04am

Hi
I have a simple question. When you're designing a tail current source (i.e. for diff pair) with let's say 10uA.
Case1:
You select a gate voltage which will keep the FET in saturation& MI-SI. i.e. 550 mV will do it. that case transistor sizes will be small like 2u/400n

Case2:
You mirror that 10uA from an ideal current source with a current mirror and select transistors sizes big i.e. 40u/400n
In that case gate voltage may be aroung 380 mV. Still in saturation but probably around WI

Which case is more suitable for a tail current source OR the any other recommendation???

Thanks

Title: Re: Tail current source sizing MI/SI vs. WI
Post by topquark on Apr 23^rd, 2007, 1:44am

Hi,
My quick thoughts on this-
For a tail current source of diff-pair, you need a certain min common-mode voltage on the gate of the diff pair to keep the tail nMOS in saturation(even if it's at the edge).
Sometimes, this isn't possible(even weak inv.) and you have to settle for a resistor in its place.

But, if you have sufficient Vgs, then, you can design to put your MOS into weak, moderate or strong inversion. Check out : http://www.designers-guide.org/Forum/YaBB.pl?num=1168276093/4#4
But, that post talks about getting 'gm' in different levels of inversion.
Is there a similar correlation for 'ro' whwich is what is required of a tail current source?

Title: Re: Tail current source sizing MI/SI vs. WI
Post by SATurn on May 5^th, 2007, 3:25am

There is also another important issue. The matching in WI is so poor! So, it is preferred to bias the tail bias transistor in SI. If you have enough headroom (400-500 mV), you can use a cascade topology ...

SATurn

Title: Re: Tail current source sizing MI/SI vs. WI ???
Post by aaron_do on May 5^th, 2007, 6:41pm

Hi,

you also want to have low gm in your tail current to minimize the noise contribution (go for SI). This is actually common mode noise and will be partly rejected due to the differential operation.

Also is the 400nm length fixed? If not you can consider increasing it for larger output resistance. This improves your common mode rejection.

cheers,
Aaron

Title: Re: Tail current source sizing MI/SI vs. WI
Post by RobG on May 7^th, 2007, 4:18pm

As you make the device wider you will increase the common mode input range because you are lowering VDSat of the tail current source, but you probably already knew that.

The main drawback hasn't been addressed: the tail node capacitance is increased, which increases AC distortion. This is very apparent if you a put a voltage step into a single-ended opamp in voltage-follower configuration. The rising edge of the output will be much faster than the falling edge because the tail capacitance adds tail current for the upward edge, but subtracts it on the falling edge.

The advice about noise (esp flicker) and mismatch in strong versus weak inversion is correct if you are changing the current to achieve these regions. BUT..... increasing the width has no effect on flicker noise or mismatch because you are increasing the device area in addition to increasing Gm. The effects cancel, until you get to WI. Then Gm stays constant while in WI so flicker and mismatch actually improve. So the wide WI current source actually matches better than the narrow SI current source. Again, the reason is that you are making the device larger to achieve WI.

Title: Re: Tail current source sizing MI/SI vs. WI
Post by aaron_do on May 7^th, 2007, 6:45pm

Hi RobG,

are you sure about the noise part? Actually i'm not so sure about the flicker noise, but for the thermal noise, gm/ID is larger in weak inversion. So i think the thermal noise should be higher.

cheers,
Aaron

Title: Re: Tail current source sizing MI/SI vs. WI
Post by RobG on May 7^th, 2007, 6:49pm

aaron_do wrote on May 7^th, 2007, 6:45pm:

Aaron,
I think you are correct about the thermal noise increasing as W gets bigger. Sorry about that.

rg