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Design Languages >> Verilog-AMS >> Hierarchy Parameter Passing - Multi Level
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Message started by loose-electron on Apr 22^nd, 2007, 11:01pm

Title: Hierarchy Parameter Passing - Multi Level
Post by loose-electron on Apr 22^nd, 2007, 11:01pm

> What is the proper syntax on parameter passing thru multiple levels of
> hierarchy in Verilog-AMS structures?

> Ergo:
> Module 1 calls module 2,
> Module 2 calls module 3,
> Module 3 calls module 4,
> Module 4 calls module 5,
> You have some "parameter real Vxxxx = XXX" statements down in module
> 5, and you would like to use a parameter override up at the module 1
> level, to define the value.
> For one level:
>
> Modulename #(.varaiblename(number)) moduleinstance(port1,port2,....);
>
> That works fine for one level of overide.
>
> The question is how to pass a variable thru multiple levels???
>
> In the above example, module-1 needs to provide a parameter override
> to module-5, and a graceful way of passing this down the hierarchy is needed.
>
> Thanks,
> Jerry

Title: Re: Hierarchy Parameter Passing - Multi Level
Post by Geoffrey_Coram on Apr 23^rd, 2007, 4:10am

I think the only way you can do that is with the defparam statement.

Eg, if module0 is your top level that instantiates module1, then you would do something like
defparam module1.module2.module3.module4.module5.Vxxxx = 5.0;

on the line after the instantiation of module1.

Title: Re: Hierarchy Parameter Passing - Multi Level
Post by loose-electron on Apr 23^rd, 2007, 1:37pm

OK, well I ended up restruturing the models to deal with it.

Something like an option with a varaible that is recognized at all levels of the hierarchy would be nice.

Title: Re: Hierarchy Parameter Passing - Multi Level
Post by chetan on May 30^th, 2007, 9:22am

You should also be able to do it without using defparam by propagating the parameter from Module 1 like this:

module module1....
parameter pass_me_down = 0 ;

module2 #(pass_me_down) inst_name ...
endmodule

module module2...
parameter I_wanna_go_down2 = 0 ;

module3 #(I_wanna_go_down2) inst_name ...
endmodule

so on and so forth.

Verilog(A) allows using parameters in the expression for the parameter override, using this feature does the trick.

-Chetan Chaudhari-