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Design Languages >> Verilog-AMS >> cascode current source
https://designers-guide.org/forum/YaBB.pl?num=1177343086

Message started by Croaker on Apr 23^rd, 2007, 8:44am

Title: cascode current source
Post by Croaker on Apr 23^rd, 2007, 8:44am

Hi, I'm pretty new to Verilog-AMS and was wondering how I can get a reasonable model of a cascode current source. I'd like to be able to have a triode and saturated mode, and a suitable output resistance. I'm not trying to re-invent the wheel here, so if a good model exists, please let me know! Thanks!

Title: Re: cascode current source
Post by Croaker on Apr 23^rd, 2007, 2:07pm

Right now I'm modeling it as a piecewise linear function...but I'm all ears if there's a better way to model it. I think I've captured the basic DC Ids vs. Vout curve, although it's pretty approximate around the point where the current starts to saturate.

Title: Re: cascode current source
Post by mg777 on Apr 24^th, 2007, 10:08am

I'm curious why you wouldn't use a Spice model. If you're using the cascode in a self-referenced source, then it makes sense to model the start-up circuit behaviorally. But I'd still keep the cascode in Spice.

M.G.Rajan
www.eecalc.com

Title: Re: cascode current source
Post by Croaker on Apr 24^th, 2007, 11:29am

The goal is to replace transistors with a simpler model for faster simulation. Verilog-A seems most useful when you're modeling a lot of transistors with some equations, but something like UltraSim with simplified transistor models is better for blocks where you want to capture the transistor characteristics.

Title: Re: cascode current source
Post by krishnap on Apr 24^th, 2007, 11:51pm

How about using the schematics in spice for normal mode of simulation and
using the tool like AMS designer to compile it , when the faster simulation
is required for the analog blocks?

Regards,
Krishna

Title: Re: cascode current source
Post by Croaker on Apr 25^th, 2007, 5:00am

Really? I didn't know the tool could do that. Right now I'm just typing in the Verilog-A, creating a symbol, and simulating from a schematic as usual.

Title: Re: cascode current source
Post by Andrew Beckett on May 8^th, 2007, 9:46pm

Not sure what Krishnap was trying to say, but a transistor level design won't run any quicker in AMS Designer than it would in spectre (unless you're using Ultrasim as the analog solver). If the solver is the same, it will take a similar time.

The benefit of AMS Designer is when you have mixed-signal models in Verilog-AMS or VHDL-AMS, and pure digital parts in Verilog or VHDL. Then you don't need to simulate everything at transistor level any more...

Regards,

Andrew.

Title: Re: cascode current source
Post by Croaker on May 8^th, 2007, 11:09pm

Yeah, I think he was saying there was a way to generate a behavioral model (V-AMS code) given a Spectre netlist. I have not found any capability like this.

Title: Re: cascode current source
Post by Andrew Beckett on May 9^th, 2007, 9:50pm

Actually Cadence has a tool "DCM" which effectively does this. It has a library of templates (which you can extend yourself using OpenDCM) and it characterises the circuit using simulation and fits a behavioural model in Verilog-A/Verilog-AMS to the measured circuit behaviour...

In IC5141 this is an extension to the Virtuoso Specification Driven Environment (sometimes known historically as "Aptivia"), and in IC61X it is part of Virtuoso Analog Design Environment GXL.

Regards,

Andrew.

Title: Re: cascode current source
Post by Croaker on May 10^th, 2007, 4:50am

Ah, very interesting! Thanks! :)