The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Can you define these MOS netlists?
https://designers-guide.org/forum/YaBB.pl?num=1177479410

Message started by hande.vinayak on Apr 24^th, 2007, 10:36pm

Title: Can you define these MOS netlists?
Post by hande.vinayak on Apr 24^th, 2007, 10:36pm

Hi to all,
I am having below given mos net lists, can anybody help me realize this...?,

1.What device does it interpret?
2.When can we use these?
3.What is the special in these devices which are form by MOS?

(drain gate source body)

Net lists..
1. in in in avdd pmos (in is an input pin)
2. on on on avss nmos (on is an input pin)
3. avdd avdd avdd avdd pmos
4. avss avss avss avss nmos
5. avss reference avss avss nmos (reference is a net)

Thnx.

Title: Re: Can you define these MOS netlists?
Post by krishnap on Apr 24^th, 2007, 11:10pm

Hi Vinayak,

From the netlsit it appears that these are nmos and pmos.
usually first four keywords are for the S G D B terminal of the MOS and
the last keyword is the MOS type. i,.e.,Which type of model to use.(PMOS, NMOS etc.,)
And the order of terminals depends on the simulator.

Title: Re: Can you define these MOS netlists?
Post by hande.vinayak on Apr 24^th, 2007, 11:34pm

Thnx Krishna,
But my doubt is these mos forms two different caps,
what is the significance of those (reference to netlist of 1,2 & 5)?

Title: Re: Can you define these MOS netlists?
Post by adesign on Apr 25^th, 2007, 9:38pm

Vinayak,

First and second line of netlist will give high ESR cap, whereas fifth line signifies low ESR cap.
Hope it clears.

Regards,

Title: Re: Can you define these MOS netlists?
Post by hande.vinayak on Apr 25^th, 2007, 11:25pm

Thnx,
As reference to last post,I am having one doubt..
Is it important to connect a high ESR cap at input terminal/pin?
What affect it will make on circuit operation if we connect low ESR cap to input terminal/pin?

Thnx n Regards.

Title: Re: Can you define these MOS netlists?
Post by adesign on Apr 26^th, 2007, 12:30am

Where do you want to connect this cap? Please elaborate on the circuit architecture.

Title: Re: Can you define these MOS netlists?
Post by hande.vinayak on Apr 26^th, 2007, 5:40am

The mentioned 'in' is a one of input of charge pump for PLL.