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Design Languages >> Verilog-AMS >> terminal of instance not found on master
https://designers-guide.org/forum/YaBB.pl?num=1177553719

Message started by Croaker on Apr 25^th, 2007, 7:15pm

Title: terminal of instance not found on master
Post by Croaker on Apr 25^th, 2007, 7:15pm

In my veriloga cell, the syntax is fine but things mysteriously break when I attempt to simulate.

ERROR: netlister : terminal of instance X in cell B, view veriloga : not found on master

My code seems pretty straightforward to me. It seems like there is a CAD tool problem more than a veriloga code problem...

module x( sig1, sig2 );
input sig1;
output sig2;
electrical sig1, sig2;

mymod X( sig1, sig2 )
endmodule

In the real code, the veriloga ports and definitions were generated automatically from the symbol view. The ports of mymod are inouts.

This one is making me pull my hair out! :'(

Title: Re: terminal of instance not found on master
Post by Geoffrey_Coram on Apr 26^th, 2007, 12:54pm

It probably won't help but:
1) give the instance of mymod a different name (XX) so it won't be a case-insensitive match for the module it's inside
2) name the port connections of that instance
3) add a semicolon to the end of the line

mymod XX(.sig1(sig1), .sig2(sig2));

Title: Re: terminal of instance not found on master
Post by Croaker on Apr 26^th, 2007, 4:48pm

Oh, don't scrutinize the syntax too carefully, just trying to convey the idea.

It turns out that it would break or not depending on what order I instantiated the instances. This makes no sense from a code point-of-view. Tools misbehave.

Title: Re: terminal of instance not found on master
Post by chetan on May 30^th, 2007, 9:33am

The names you're trying to use for the module - 'X' and instance - 'x' are both reserved keywords. I bet, that's the reason why the tool is completely confused!

Title: Re: terminal of instance not found on master
Post by chetan on May 30^th, 2007, 9:36am

Sorry, I should have qualified that these keywords are reserved for the digital part of Verilog-AMS or in Verilog-HDL. The yare reserved as binay/octal/hex digit specification to convey that the value is unknown. Try just changing these names.