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Design Languages >> Verilog-AMS >> string variables in VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1177696583

Message started by makelo on Apr 27^th, 2007, 10:56am

Title: string variables in VerilogA
Post by makelo on Apr 27^th, 2007, 10:56am

I want to improve the VerilogA file that I use to write data to a text file. The current version works but does not allow me to change the file name during execution of the program. I tried using the the STRCAT function to concatenate a two strings but that does not work.

Here is what I currently have that works.

`include "disciplines.vams"
`include "constants.vams"

module sink_IQ(vi,vq);
electrical vi,vq;
parameter string file_name = "dat1_out.tbl";
parameter real T_step = 1e-9;
integer file_ptr, hdrPrinted;

analog begin
@( initial_step ) begin
file_ptr=$fopen(file_name);
end

@(timer(0,T_step)) begin
$fwrite(file_ptr, "%e %e %e\n", $abstime, V(vi), V(vq));
end

@ (final_step) begin
$fclose(file_ptr);
end
end
endmodule

I would like to add a line like
file_name = strcat(file_name,suffix);
within the code to allow me to change the file name. Is there another way to do this?

Thanks,
Makelo

Title: Re: string variables in VerilogA
Post by Geoffrey_Coram on Apr 30^th, 2007, 4:13am

I see in this thread: http://www.designers-guide.org/Forum/YaBB.pl?num=1177697346
you've tried passing the parameter and had trouble.

The AMS committee is presently considering extensions to the language to support the sorts of things you want to do, but I'm not aware of any simulator that allows you to do it now (sometimes, extensions are "donated" by a company that already supports the new feature).

Title: Re: string variables in VerilogA
Post by chetan on May 30^th, 2007, 11:49am

The concatenation operator addresses your need.

Example:

`include "constants.h"
`include "discipline.h"

module add_str( in1, in2 );

input in1, in2;
electrical in1;
electrical in2 ;

parameter string filename = "foo" ;
parameter string file_ext = ".bar" ;
string concatenated ;

string var1 ;
string var2 ;
string concat_var ;

analog
begin
V(in1,in2) <+ I(in1,in2) ;
concatenated = { filename, file_ext};
$strobe("concat from params:%s ", concatenated ) ;

var1 = "car" ;
var2 = ".shar" ;
concat_var = {var1, var2} ;
$strobe("concat from vars:%s ", concat_var ) ;
end
endmodule

Title: Re: string variables in VerilogA
Post by Geoffrey_Coram on May 31^st, 2007, 3:44am

chetan -
Unfortunately, string variables are not part of the Verilog-AMS LRM:
string concatenated;

is not legal Verlog-AMS.

Also, having recently read the SystemVerilog LRM section on strings, it talks about assigning string literals or string types to string variables; is a concatenation of string types a self-determined expression of string type?