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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> Passing Strings to VerilogA in ADS https://designers-guide.org/forum/YaBB.pl?num=1177697346 Message started by makelo on Apr 27th, 2007, 11:09am |
Title: Passing Strings to VerilogA in ADS Post by makelo on Apr 27th, 2007, 11:09am I have a VerilogA function that I use in ADS to read CSV data into the ADS time-domain simulator. I use a verlogA block to read the data and an ADS "ael" code to create the interface between verilogA and ADS. This is what I currently use, that works but does not pass the string "File_name": -----VerilogA------------- `include "disciplines.vams" `include "constants.vams" module Source_IQ_va(n1); electrical n1; parameter string File_name = "dat2I.tbl"; parameter real max_time_step = 1.0e-9; analog begin V(n1) <+ $table_model($abstime,File_name,"1L"); $bound_step(max_time_step); end endmodule --------------------------------- ---------ADS AEL-------------- /* AEL discription of Source_IQ_va */ create_item("Source_IQ_va", /* Instance name */ "Verilog-A implementation of CSVsource", /* Component description */ "Source_IQ_va", /* Instance prefix */ NULL, NULL, "Source_IQ_va", standard_dialog, "*", ComponentNetlistFmt, "Source_IQ_va", ComponentAnnotFmt, "SYM_Source_IQ_va", no_artwork, NULL, ITEM_PRIMITIVE_EX, create_parm("File_name","Maximium Time Step in BoundStep", PARM_OPTIMIZABLE | PARM_STATISTICAL, "StdFileFormSet", UNITLESS_UNIT, prm("StdForm","1.0")), create_parm("max_time_step","Maximium Time Step in BoundStep", PARM_OPTIMIZABLE | PARM_STATISTICAL, "StdFileFormSet", UNITLESS_UNIT, prm("StdForm","1.0")) ); ---------------------- My question is how do I change the AEL code to make ADS actually pass a string. Right now I have to manually change "File_name" in the verilogA for every new simulation. I think it has something to do with the create_parm function? Thanks, Makelo |
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