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Simulators >> Circuit Simulators >> decrese the simulation time of large circuit
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Message started by mosman on Apr 28^th, 2007, 7:18pm

Title: decrese the simulation time of large circuit
Post by mosman on Apr 28^th, 2007, 7:18pm

it is well-known that simulating large circuit especially mixed circuit will be very time-consuming, for example, one day, two days,.... can anyone use some special methods to accelerate the simulating? or some new revolutions in new EDA softwares?

in the top simulayion of one large circuit we want to simulate all spec of this circuit. but if one function is finished in one day it is terrible to go through all spec. so i think a new method should be applied to the situation. maybe you can share your experience on this with us.

let's improve our skill in designning circuits!
:D

Title: Re: decrese the simulation time of large circuit
Post by ywguo on Apr 28^th, 2007, 11:55pm

Hi, mosman,

You'd better think over some techniques that reduce the simulation time accordint to your specific circuit. I think that depends on your design.

However, there are some general guide, too.

Only save the voltages/currents that you want to measure.
Replace some complex circuit with ideal model like verilog-a model.
Simulate the related circuit only, NOT the whole chip, for some specs if possible.

Yawei

Title: Re: decrese the simulation time of large circuit
Post by mosman on May 28^th, 2007, 11:43pm

ywguo wrote on Apr 28^th, 2007, 11:55pm:

Only save the voltages/currents that you want to measure.
Replace some complex circuit with ideal model like verilog-a model.
Simulate the related circuit only, NOT the whole chip, for some specs if possible.

Yawei

Thanks Yawei very much!
1. yes saving less number of v/I will save time.
2&3. i am afraid that verilog-a model should use at the strat of project. when in the end of one project we want to verify all specs. so we should combine one block with others. it will increase the simulation time.

recently i learned a method to simulate some large circuits which consist of feedback loop. the new method is named open simulation (maybe :( ) this method is to open the loop of the circuit to verify some specs such as over voltage, over current, and so on. due to no feedback the method save much time compared with the old closed verify method. but i think acctually this circuit is running at open situation. is it different with the normal situation? under such case the result is right or wrong? can i trust the results?

do anyone know more infomation about this method? and do you think about this method?

Title: Re: decrese the simulation time of large circuit
Post by Ken Kundert on May 29^th, 2007, 12:03am

Take a look at http://www.designers-guide.com/docs/cicc06-dgc.pdf.

-Ken

Title: Re: decrese the simulation time of large circuit
Post by mosman on May 29^th, 2007, 7:40pm

thanks Ken. i am going through your paper now.