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Design Languages >> Verilog-AMS >> current source convergence issues when open
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Message started by Croaker on Apr 30^th, 2007, 7:52pm

Title: current source convergence issues when open
Post by Croaker on Apr 30^th, 2007, 7:52pm

Let's say I make a simple ideal current source, e.g. I( p, n ) <+ IDC.

How do I make it such that there aren't convergence issues when it's open? You know, the voltage blows up if it's trying to make current flow into an open.

Title: Re: current source convergence issues when open
Post by Geoffrey_Coram on May 7^th, 2007, 4:31am

One way would be to put GMIN in your model:
I( p, n ) <+ IDC + $simparam("gmin", 1e-12) * V(p,n);

There isn't a GMIN in most simulator's ideal current sources, though. Why do you want one?

Title: Re: current source convergence issues when open
Post by Croaker on May 7^th, 2007, 5:03am

Thanks!

I want one because I have a big circuit block and sometimes some of the pins won't be connected.