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Design >> Analog Design >> Bandgap reference transient analysis
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Message started by chungmnig on May 1^st, 2007, 7:02pm

Title: Bandgap reference transient analysis
Post by chungmnig on May 1^st, 2007, 7:02pm

Hi ~~
I have a question about bandgap reference
Like attached picture
This is my transient analysis result (simulate vdd off and on conditions)
Why the bandgap voltage overshoot is so large?
(regardless there has start up circuit or not……)
My opamp is well designed.
(gain 80dB, phaseMargin 70, UGF 700kHz ,slew rate 0.8M V/s
and bandgap loop gain 80dB, loop phaseMargin 65, loop UGF 350KHz)

Thanks ~!!!!!

Title: Re: Bandgap reference transient analysis
Post by Visjnoe on May 1^st, 2007, 11:43pm

Dear Chungmnig,

I think it is so big because of the top right capacitor...when VDD goes high/switches, you will basically see a spike which is determined by the ratio between this capacitor and the capacitor to ground. So basically, removing the top right capacitor (or changing this ratio) will seriously improve this issue.

As a side remark, I don't think that the voltage you are generating (VBG) is a bandgap voltage.

Regards

Peter

Title: Re: Bandgap reference transient analysis
Post by hspice on May 2^nd, 2007, 3:36am

Agree with Peter. Also, you may let power ramp up other than step up. Such step up may make you missing potential start up problem.

Regards

Title: Re: Bandgap reference transient analysis
Post by RobG on May 3^rd, 2007, 5:19pm

I can't think of any good reason to have a cap from Vdd to your output, but I don't think it is causing the overshoot.

I think it is just the response time of the opamp... Upon startup, the op-amp output will be forced to the bottom rail by the startup circuit. That will pull your BG output to the top rail. The opamp's bandwidth suggests response times on the order of uS, and that is what you are seeing.

In addition, your particular compenstation scheme will cause overshoot in response to Vdd changes. This isn't obvious, but consider this: Your opamp compensation is referred to the bottom rail. If the top rail has a high-speed step, the gate-source voltage of your PMOS mirrors will change by the same amount (the compensation prevents the opamp from changing quickly), and you will see a big bump on VBG. You would have to redesign the opamp to get around this (e.g. a folded cascode with compenstation from output to positive rail). If you do this I think you will have better startup characteristics.

Title: Re: Bandgap reference transient analysis
Post by anhnha on Jun 9^th, 2014, 11:51pm

Hi, could you tell me how to simulate loop gain for that bandgap?
I meant how you set up the testbench and how to simulate it in Cadence.
Thanks.

Title: Re: Bandgap reference transient analysis
Post by cchen on Jun 12^th, 2014, 2:51am

You may use stb analyis of spectre.

anhnha wrote on Jun 9^th, 2014, 11:51pm:

Hi, could you tell me how to simulate loop gain for that bandgap?
I meant how you set up the testbench and how to simulate it in Cadence.
Thanks.

Title: Re: Bandgap reference transient analysis
Post by raja.cedt on Jun 12^th, 2014, 7:30am

Hi chungmnig,

1.Try to keep decaps across Gate and source which eliminates any supply leakage through gm component.
2.Please re-design opamp with nmos input pair which reduce systematic offset and supply rejection.
3. In your case capacitor at the o/p and between vdd and o/p may act like a divider. Check the division ration. If there is no special reason please remove top cap.
4. Since you are changing Vdd from 3.3V to 0V, I don't think small signal stability will work perfectly here, I have seen some earlier some ckts showing good PM but they start oscillating after certain level of vdd step. Just to make sure there is no problem with stability change the vdd step to 100mV and see how things are going, if you still have the same problem then you have stability.
5. Please try to reduce rise and fall times of vdd switching, which may reduce un-necessary coupling.

Raj!!!