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Design Languages >> Verilog-AMS >> questions about the cadence pll library
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Message started by calven on May 1^st, 2007, 11:33pm

Title: questions about the cadence pll library
Post by calven on May 1^st, 2007, 11:33pm

hi！experts!
i am learning the tuition of the pll library in cadence.here are some questions:
1.why we need (1-k) two times in the model equation of the duty cycle?
2.in this library,jitter and spurs are not mentioned.is it possible to simulate these with verilog-a?
3.the duty cycle may be larger than 1 at dc analysis,but it will always be equal or less than 1 at transient analysis?i feel that the real duty cycle can never be larger than 1.
give me some advice.thanks a lot

Title: Re: questions about the cadence pll library
Post by couragebo on May 16^th, 2007, 9:50am

hi, I try to answer your first question :)

1. You can see that the (1-k) outside the integration is for the case of small frequency error( (1-k) --> 1) . As to (1-k) inside the integration, I think it is to put the integration 'sleep' when frequency error is large. Note the integration with reset, which means once the phase exceeds 2*pi, the integration will reset. This reset could be useless for the large frequency errors( (1-k) --> 0 ), because in this case we consider only the k*H part, not the integration part. So (1-k) is put into the integration to make the reset happen non-frequently. At the same time it has no effect for small frequency error, as (1-k) --> 1.

Title: Re: questions about the cadence pll library
Post by Jess Chen on May 16^th, 2007, 11:03am

1. couragebo is correct about the factor of (1-k).

2. Jitter and spurs are indeed not mentioned in the pllLib documentation. However, since writing those models I have successfully used them to simulate nonlinear phase noise effects and idling spurs in a fractional-N synthesizer. The real trick is to get all the injected noise levels correct.

3. You are absolutely right about the duty cycle never being greater than 1. I allowed the duty cycle to be greater than 1 for DC analysis to trade useful results for convergence errors. If you do not let the duty cycle exceed 1 for DC analysis and the DC conditions do not support a locked state, the DC analysis will fail to converge and you get no useful information. However, if you let the duty cycle exceed 1 just for DC, an accessible operating point always exists. It is true, that the point to which the simulation converges is not real, but at least now you have results that point to the source of your problem instead of a cryptic message about non-convergence. The only drawback is that you have to remember to check the duty cycle before putting any faith in subsequent analyses.