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Design >> Analog Design >> Latchup Guidelines
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Message started by Faisal on May 10^th, 2007, 8:24am

Title: Latchup Guidelines
Post by Faisal on May 10^th, 2007, 8:24am

Hi all,

I am working on 0.18 um CMOS bulk process. The problem is that the foundry we are using has not developed the latchp up guidelines for this process yet.

What general guidelines should I follow?

Title: Re: Latchup Guidelines
Post by ywguo on May 10^th, 2007, 7:49pm

Hi, Faisal,

The latch-up is explained in many textbooks. Here are some general guidelines to prevent latch-up.

Put guard ring between NMOS and PMOS.

Put NMOS and PMOS far away from each other.

Put pickup OD (that means vdd or ground) near NMOS and PMOS.

Because the large current flows through I/O buffers, the first two guidelines must be applied in I/O buffer layout. For core devices, normally only the last guidelines are required. For 0.18um, the nearest pickup OD to NMOS/PMOS should not greater than about 25um generally.

BTW, which foundry is your 0.18um process from? :) I would not like to use such a process without latch-up guidelines. You'd better ask the foundry and confirm.

Yawei

Title: Re: Latchup Guidelines
Post by krishnap on May 14^th, 2007, 4:38am

some practises followed are:

All the devices connecting to the Pad should have Double guard ring.
Double guardring means that substrate contact ring(substrate tap or nwell) surrounding the device and
other opposite type( P or nwell) surrounding the first ring.

All the devices related to the I/O buffers will have double guard ring.

Other devices close to the I/ O's say within 100um should see the substrtae tap within 5 to 10um,
and substrate contacts in the form of ring is prefeerable.

Also the width of substarte ring and number of rows of conatcts are more , compared to other devices far away,
or not latchup immune.

Also, Substrate contacts are drawn for every 25um interval.