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Design Languages >> Verilog-AMS >> How to instantiate spectre modules in VerilogA ?
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Message started by rajdeep on May 10^th, 2007, 9:56pm

Title: How to instantiate spectre modules in VerilogA ?
Post by rajdeep on May 10^th, 2007, 9:56pm

Hi all,

I'm trying to instantiate one spectre module within a VerilogA netlist. But it is giving a parse error, saying
that the instantiated module is undefined.

I'm trying to write model for a big module M which contains another module B.
I'm trying to model M actually. To do this I'm just instantiating B whose schematic and symbol views both are available
in the same library. (I'm using Cadence ICFB environment .)

Is there a way to instantiate a symbol within a verilogA? Because I'm only following the method of instantiating subckts
and it is not working.

Plz help!
Rajdeep

Title: Re: How to instantiate spectre modules in VerilogA
Post by Andrew Beckett on May 12^th, 2007, 2:31am

Do you have veriloga in the stop list of the netlister (Setup->Environment)? If so, it shouldn't be, since there is hierarchy within the veriloga view. Note, the same thing applies if you're using a config - veriloga should not be in the stop list in the config.

Is the subckt for B appearing in the netlist?

Try modifying the veriloga view for M (add a blank line) and save and exit the editor - this will re-trigger it to be parsed, and it should then update the cellView with information about the hierarchy. Provided you're using IC5141 or earlier, you might want to look in library directory structure, under the cellView M/veriloga, and look at the file pc.db. This file should indicate any cellViews instantiated within M - and this is how the hierarchy expansion at netlisting time knows to netlist B. The pc.db file is ASCII, so can be inspected easily (don't edit it though...)

Regards,

Andrew.

Title: Re: How to instantiate spectre modules in VerilogA
Post by rajdeep on May 31^st, 2007, 11:13am

Hi Andrew,

thanks again! I haven't checked that. This seems to be the reason..

Rajdeep