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Simulators >> Circuit Simulators >> rise and fall time of an ideal ADC
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Message started by ywguo on May 12^th, 2007, 1:46am

Title: rise and fall time of an ideal ADC
Post by ywguo on May 12^th, 2007, 1:46am

Hi, Guys,

I use an ideal ADC to quatize sine wave of ramp signal when I simulate a current-steering DAC. The ideal ADC is written in Verilog-A and modified based on the 8-bit ideal ADC (adc_10bit_ideal) in ahdlLib. I increased the number of bit to 10, and lower the transition voltage to 0.9V. The rise and fall time defined are both 0. However, I simulated using Spectre and the rise and fall time are both 18ns. It caused some errors in my simulation.

Because I cannot copy the file from company's workstation, I rewrite some of the file below.

// adc_10bit_ideal
//
// vin: [V,A]
// vclk: [V,A]
// vd0..vd9: data output terminals [V,A]
//
// Instance parameters
// tdel , trise, tfall = {usual} [s]
// vlogic_high = [V]
// ...
// vtrans_clk = clk high to low transition voltage [V]
// vref = ...

module adc_10bit_ideal(vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk);
electrical vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vlogic_high = 1.5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 0.9;
parameter real vref = 1.0;

`define NUM_ADC_BITS 10
real unconverted;
....

// assign the outputs

V(vd9) <+ transition ( vd[9], tdel, trise, tfall );
...

`undef NUM_ADC_BITS
end
endmodule

What's wrong with my simulation? Any comments are appreciated.

Best regards,
Yawei

Title: Re: rise and fall time of an ideal ADC
Post by Andrew Beckett on May 12^th, 2007, 2:20am

Circuit simulators cannot handle zero rise time - that's a discontinuity in value, and the poor simulator would have to try to resolve an infinitely small timestep to be able to do so.

So give it a reasonable rise time. I can't remember exactly what happens, but I suspect you just end up with a random rise time which is dependent on what else happens in the circuit, if you do what you're doing.

Note also that there is a limit to the minimum transition time - this is a fraction (1e-9 if my memory is correct) of the simulation interval (typically the stop time), which is to ensure that there is sufficient margin to resolve transitions when the time is large (because you get close to running out of numerical resolution with a double precision number otherwise). This however is normally only a problem with large stop times (e.g. 1 second) with short transitions (e.g. less than 1ns). There's also a transient option (see spectre -h tran) which allows you to tweak the resolution (I think it's called transres or something like that).

Regards,

Andrew.

Title: Re: rise and fall time of an ideal ADC
Post by ywguo on May 12^th, 2007, 2:41am

Andrew,

My stop time of .tran is not so long. It is from several us to tens of us.

I put some non-zero value in the parameters of the ideal ADC. It works fine. Thanks.

The instantiation is shown below.

I7 (DATA_9 DATA_8 DATA_7 DATA_6 DATA_5 DATA_4 DATA_3 DATA_2 DATA_1 DATA_0 VIN CLK) adc_10bit_ideal trise=0.5n tfall=0.5n tdel=0

Best regards,
Yawei