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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Re: cascode on paper/cadence https://designers-guide.org/forum/YaBB.pl?num=1179131884 Message started by aaron_do on May 14th, 2007, 7:32am |
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Title: Re: cascode on paper/cadence Post by aaron_do on May 14th, 2007, 7:32am Hi, your transistor may be operating in the triode region.Also your equation for Av looks wrong (there should be a gm1 there somewhere). Aaron |
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Title: Re: cascode on paper/cadence Post by .matteo on May 14th, 2007, 7:59am hi all! I would like to design a cascode configuration and my target are: - gain ≥ 20 - Vout DC ≈ 1.8 volt I calculated some values on paper and I simulated my circuit but the results are completely different! my circuit is here: http://www.thebags.it--out-of-date/listing/uni/cascode.png if I want Vout = 1.8V Rd*Id = 1.5V; Rd = 600ohm so Id = 2.5mA if I want Av = gm2 * (Rd//r02) = 20 I have to choose Vov = 0.10V and so Vgs = 668mV if I want Id = 2.5mA and Vov = 0.10 W has to be W=1080u ...I set these values in cadence but the risult is completely different! Can you try to explain me why? any help is appreciated thank you (and sorry for my english..) |
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Title: Re: cascode on paper/cadence Post by .matteo on May 14th, 2007, 8:04am aaron_do wrote on May 14th, 2007, 7:32am:
I checked the transistors conditions and they are in saturation region (because Vout is bigger than Vov1 + Vov2) what should the gain be? I thought it was 1 from the input to the source of the upper mosfet and then gm2*Rout.. however I found an error ..I polarized the second mosfet with the same Vgs of the first! but the source of the second is not connected to the ground :-? |
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Title: Re: cascode on paper/cadence Post by aaron_do on May 14th, 2007, 6:54pm Hi Matteo, I meant the bottom transistor. The VDS is only 0.047 V. And VGS is 0.668 mV. So the bottom transistor is either in weak inversion, or triode region depending on your VT. The gain would be 1 from gate to drain of the bottom transistor only if both transistors have the same gm. The cascode transistor has the effect of increasing the output resistance. If you read "design of analof CMOS integrated circuits" by rasavi, I think it shows somewhere how to calculate the gain. It should be something like: Av = gm1 . [( r01+r02 + (gm1 +gm2).r01r02)//RD] Anyway if you want more gain you should definately increase the gate bias voltage of your cascode transistor. |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 18th, 2007, 3:22am hello has all, PLEASE you can describe me precisament the operation of my mixer, knowing that transistor OL work in commutation (swith). the diagram of my mixer is in this image attached thank you beucoup for you and I awaits your answers! (excuse my for my english!!) |
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Title: Re: cascode on paper/cadence Post by Ken Kundert on May 18th, 2007, 9:10am Berberephone, Please do not change the topic of a thread. It is much better to simply start a new thread. Please read and follow the Forum Guidelines (http://www.designers-guide.org/Forum/guidelines.html). -Ken |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 20th, 2007, 3:29am hello with all, good I make a point of expressing you my excuses in worms of deposited subjects one can vagus like it said our moderating friend of the Web site, really I am sorry. good I now ask you to help yourselves in my probème which is: I have mixer with 3 ports and I wanted to make an adaptation by the parameters S, I do not know then how I can modelled or how given the matrix S holding in account of these 3 ports?? I do not know is what I answered your request or not!!! thank you to help me my friends . |
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Title: Re: cascode on paper/cadence Post by didac on May 20th, 2007, 11:42pm Hi, If you have the S parameters matrix, the diagonal parameters(S11,S22,S33) are the reflection coefficient at ports 1,2,3 respectively. With these data you can find the input impedance of each port(which is directly related with reflection coefficient). When you have the input impedance you can design a matching network using discrete components or transmission lines(ustrip or coplanar usually). Take a look at: http://www.sss-mag.com/pdf/AN154.pdf |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 26th, 2007, 3:46pm ok thank you for your answer, it is necessary that you Mister knows that I work with simulator ELDORF is not ADS this last assistance to found and has to conceive a network matched by using biensur the components, therefore yes really I makes simulatiosn and the extraction of S11, S22, S33 and the impedance of entry but I do not arrive found the network exact. you can find me the network; if you software ADS has; by sending the values of various mésures to you?? thank you Mister for your assistance and I excuse myself for the disturbance |
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Title: Re: cascode on paper/cadence Post by didac on May 27th, 2007, 11:28pm Hi, I didn't use ADS usually also, but you don't need it to calculate a matching network with transmission lines once you have the impedances. Here's a link for the best tool to design matching networks with transmission lines: http://ieee.engsoc.org/v2.0/resources/smithchart/smithchart.pdf. As a teacher tolds me years ago:"You won't be a Microwave/RF Engineer unless you know how to use this piece of paper" Good Luck, |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 29th, 2007, 2:41am ok thank you very much does not worry you my friend the lines of transmissions I do not use them in my case, I speak to you on the passive networks… to go thank you dear professor ;) |
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Title: Re: cascode on paper/cadence Post by didac on May 29th, 2007, 3:04am Hi, Sorry, I assumed that you want a matching with transmission lines. Try this website:http://home.sandiego.edu/~ekim/e194rfs01/jwmatcher/matcher2.html, I've found this web a couple of years ago when I was designing a PCB but finally I didn't use it so I can't guarantee the results accuracy, maybe it could help you. It's pretty easy to use and give you several options to play with, Good luck, PS: don't call me professor please, i'm just a grad student. |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 29th, 2007, 9:01am ok thank you very much my friend, this site I breadth already, I will like to know if you have some files with regard to the theory of dual-gate mixer (2 transistors cascode) to provide them to me stp because until now I do not arrive has to include/understand his theory. thank you and other correspondences my friend has me I am in 2nd year of DESS systems of telecommunications and micro-electronics |
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Title: Re: cascode on paper/cadence Post by BERBEREPHONE on May 30th, 2007, 8:24am ok thank you, please I will ask you for a solution has a thing: I have a problem with regard to the polarization of my transistors for dual mixer gate (OL in linear zone and RF in zone saturee) for that I use the mirrors of current to make polarize them but I do not arrive has to operate them effective menieres of such kind to polarize transistor LO by a signal close to his Vth, I signal DIDAC that I work with the food 1.2V and in a technologie065nm and with ELDORF. stp if you can give me exactly dimensions of different the values from components (W, L and resistances) has fine to operate my transistors in their zones of operation. mixer thus must work as follows: - transistor OL in top works as switch (linear) - transitor RF in bottom works in saturation I will not forget you your assistance DIDAC and I excuse myself for the disturbance. I see sending in file attaches the structure of my dual mixer gate I waits has you answer and your remarks!! |
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