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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> join strings https://designers-guide.org/forum/YaBB.pl?num=1179252782 Message started by Croaker on May 15th, 2007, 11:13am |
Title: join strings Post by Croaker on May 15th, 2007, 11:13am How do you join strings with Verilog-A? str1 = "a"; str2 = "b"; I want to have str3 = "ab". |
Title: Re: join strings Post by Geoffrey_Coram on May 16th, 2007, 7:29am You can't do this presently, not least because Verilog-A doesn't really have strings in the first place. Verilog-AMS has "string literals" from digital Verilog, which can be stored in "reg" variables (registers) of 8 bits per character, and these registers act as though they are integers. Verilog-A specifically excludes reg. |
Title: Re: join strings Post by DReynolds on May 17th, 2007, 10:19am Croaker, as mentioned, the language really doesn't deal with string manipulation: I have found it easier to do my string manipulations in another language (python, perl, skill) and then just dump it into a file that I stitch into the veriloga. David |
Title: Re: join strings Post by chetan on May 30th, 2007, 11:55am Verilog-A does allow string variables ( plane variables - apart from the registers ) as well as parameters. The string parameters are treated differently than variables. For joining the strings the concatenation operator works. I've already anwsered a similar post titled ' string variables in Verilog-A'. See if this link works: http://www.designers-guide.org/Forum/YaBB.pl?num=1177696583 That post gives an example. |
Title: Re: join strings Post by Geoffrey_Coram on May 31st, 2007, 3:47am chetan wrote on May 30th, 2007, 11:55am:
No, it doesn't -- it's not part of LRM 2.2. The V-AMS committee is working to include them in LRM 2.3, based on the definition in SystemVerilog. Perhaps your simulator has an extension that allows string variables? |
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