The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Binary counter in VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1179481023

Message started by Vabzter on May 18^th, 2007, 2:37am

Title: Binary counter in VerilogA
Post by Vabzter on May 18^th, 2007, 2:37am

Hi all,
I am trying to write a 10 bit binary counter in verilogA. I am new to verilogA and so dont know much. Can anyone please let me how to start? My idea is to run a for loop from 0 to 1023 and then convert this to binary. But not sure how to implement this...
Any help on this..
Thanks a lot
Vabzter

Title: Re: Binary counter in VerilogA
Post by Geoffrey_Coram on May 18^th, 2007, 8:43am

You could start by piecing one together from the DFF model and gates on this site. See the "Verilog-AMS" in the upper right? Click there.

Hey! there's actually a counter in theV-AMS section. Don't know what simulator you are using, nor why the counter model here needs V-AMS rather than just Verilog-A. But it's probably a reasonable starting point.

Title: Re: Binary counter in VerilogA
Post by makelo on May 22^nd, 2007, 6:55am

Here is a VerilogA counter that I recently wrote. I hope it is helpful.

`include "disciplines.vams"
`include "constants.vams"
`define N_Counts 5
`define N_offset 0
// Counter counts N_Counts and provides a pulse every N_offset counts
// Pulse is width of clock
module Counter1(rst,clk,out);
input rst,clk;
output out;
voltage rst,out,clk;

parameter real max_out = 1.2;
parameter real edge_time = 0;

real vout,clk_pulse;
integer count,clk_shape;

analog begin
@(initial_step) begin
count = -1;
end

@(cross(V(rst)-0.6,+1)) begin
count = -1;
end

@(cross(V(clk)-0.6,+1)) begin
count = count + 1;
clk_shape = 1;
if (count > (`N_Counts-1))
count = 0;

clk_pulse = (count == `N_offset) ? max_out : 0;
end

@(cross(V(clk)-0.6,-1)) begin
clk_shape = 0;
end

V(out) <+ transition(clk_pulse*clk_shape,edge_time,edge_time);
end
endmodule