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Design >> Analog Design >> Mismatch, Finger based vs unit sized
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Message started by Faisal on May 22^nd, 2007, 2:52am

Title: Mismatch, Finger based vs unit sized
Post by Faisal on May 22^nd, 2007, 2:52am

The FAB data-sheets usually specifiy the Pelgrom co-effiecient and some diagrams for the mismatch of MOS, resistors etc. On the x-axis usually the area is specified and the y-axis gives the mismatch in %age.

My question is that while estimating random offsets from this data, should I use the finger size or the absolute size of the component i.e. finger size * finger width ?

e.g 40um by 2um transistor could be realized by 4 fingers of 10um each.

Title: Re: Mismatch, Finger based vs unit sized
Post by didac on May 22^nd, 2007, 3:04am

Hi,
I think you should use the absolute width of the device. My way of thought is the following: interfingering patterns(i.e divide the transistors in multiple fingers and over the same active area put the two transistors of a current mirror) is a usual technique to reduce mismatch without a huge area increasing(like in common-centroid technique), so if mismatch its related to relative width(i.e finger size) you won't obtain any advantatges of using multifingered active areas.

Title: Re: Mismatch, Finger based vs unit sized
Post by krishnap on May 22^nd, 2007, 5:49am

Also, you may refer to the Pelgrom's law(equaion), where it specifies how the factors
like area contribute to the mismatch.

Title: Re: Mismatch, Finger based vs unit sized
Post by Faisal on May 22^nd, 2007, 6:36am

Let me explain my question a bit more. It looks to me that there are two possibilities for calculating the offset from Pelgrom equation.

1) I put in the area of an individual finger, estimate the mismatch and multiply this by number of fingers to get the overall offset.
2) I take the area of the complete transistor (finger size * number of figures) and estimate the mismatch.

Title: Re: Mismatch, Finger based vs unit sized
Post by didac on May 22^nd, 2007, 11:33pm

Sorry for the delay,
I think that the best way is to ask directly to your foundry, I checked my docs of my processes and I'm pretty sure it's W absolute but I don't know if its a general rule of the industry or not. I'm sorry but I think I cannot tell you so much due to the NDA...
Good luck

Title: Re: Mismatch, Finger based vs unit sized
Post by Faisal on May 23^rd, 2007, 6:38am

Well, I also think that the foundry documents specify the absolute width. My confusion stems from the fact that what if this pair of transistors is realized in a different way e.g. varying the number of fingers to make the layout compact etc. What effect it would have on the matching if any ??

I am trying to get an explanation in terms of random variables here. E.g. m,atching of two 40um transistors (absolute width) vs two (10um * 4 fingers) and interdigitated.
Any help would be appreciated.

Title: Re: Mismatch, Finger based vs unit sized
Post by krishnap on May 23^rd, 2007, 7:02am

I feel in the first case, with absolute width, offset of the individual transistor is lesser,
If we take two devices (matching devices) then offset contributed due to the combination is more.
In the second case, offset of the device with split fingers might be more, but relative offset
due to matcing devices is lesser than th e first case.
Most of the scenarios, prefer for ratio between two devices rather than individual device.
Any views regarding this?

Title: Re: Mismatch, Finger based vs unit sized
Post by RobG on May 23^rd, 2007, 12:27pm

Faisal wrote on May 23^rd, 2007, 6:38am:

Faisal, at least to first order, it doesn't matter. Only the total gate area is important. Take a close look at Pelgrom's paper. Using his equations you should get the same answer if you use two devices or one device with twice the area. Fingering beyond what is needed to common centroid a device pair doesn't buy you much.

rg

Title: Re: Mismatch, Finger based vs unit sized
Post by loose-electron on May 23^rd, 2007, 5:30pm

If someone could email me the paper, I would be curious. But don't take a theoretical analysis of matching too seriously.

The empirical is what matters. Measured data in the lab. I have seen enough lab data here to not take any math analysis too seriously.

Sorry, but there are a LOT of junk equations in the electronics world. They get put forth as academic tools to help people understand whats going on. Everyone starts to treat them as a divine truth and ignore the set of restrictions and conditionals that made those academic simplifications viable. :o

That said -

Some quick and simple - Guidelines for matching:

Get lab data from the foundry.

Larger geometry means better matching, with channel length being one of the major contributors. (Especially true at 130nm and below, and through the use of halo techniues and angular ion impants.)

Best to use channel lengths longer than 3X minimum channel length.

Best to use common centroids for differential pairs.

Best to interdigitate circuit elements and use perimeter dummies.

my 2 cents worth...
Jerry

Title: Re: Mismatch, Finger based vs unit sized
Post by RobG on May 25^th, 2007, 9:56am

loose-electron wrote on May 23^rd, 2007, 5:30pm:

If someone could email me the paper, I would be curious. But don't take a theoretical analysis of matching too seriously.

The paper I was talking about is just the classic JSSC 1989 " Matching properties of MOS transistors" paper by Pelgrom. The take-home message was that mismatch standard deviation decreases with the square root of area. You still need to find the proportionality constants empirically, although they are related to process (oxide thickness, etc). The constants shouldn't change with device sizes, but many things make them look that way (See Drennan's JSSC paper) so it may be best to get mismatch data for the device sizes of interest if they are close to minimum sized devices.

Current factor mismatch can be tricky because strain can change it... .but most designs are more sensitive to Vt mismatches. I've had very good success predicting mismatch performance using the principles outlined by Pelgrom... kinda made a career out of it, actually.

rg

Title: Re: Mismatch, Finger based vs unit sized
Post by loose-electron on May 25^th, 2007, 2:20pm

Quote:

The paper I was talking about is just the classic JSSC 1989 " Matching properties of MOS transistors" paper by Pelgrom. The take-home message was that mismatch standard deviation decreases with the square root of area.

Current factor mismatch can be tricky because strain can change it... .but most designs are more sensitive to Vt mismatches.

Oh, ok, I saw that paper many moons back, but truth be known, beyond a certain area, the matching does not improve significantly. Law of diminishing returns so to speak. Too much empirical data out there. If you have nothing else to go with, its a good first shot "educated guess approach" - As I am a reviewer for the JSSC, I don't take everything there as gospel, both good and (some) bad survive the review process and a lot of it becomes invalid for newer technology.

Current mismatch vs. threshold mismatch? I have always seen these as just two different ways of looking at the same thing. Hold the Vgates the same, look at the differenc in Idrain, -- or -- hold Idrains the same and look at the difference in Vgate.

Title: Re: Mismatch, Finger based vs unit sized
Post by RobG on May 25^th, 2007, 2:51pm

I figured you saw the paper before...

I don't know who coined the confusing term "Current Factor," but it is different than what you are thinking. Currrent factor mismatch is referring to mismatch in β, that is, μC_OXW/(2L). As you may know, you can lump the mismatch causes into two groups: mismatches in Vt, which are most important, and mismatches in "other stuff." To make life easy the "other stuff" is lumped into a β "current factor" mismatch and we then assume it is independent of the Vt mismatch.

β mismatch is usually not important, but its standard deviation can increase with plastic packaging because silicon strain affects mobility (μ). That stress (and thus the mobility) can also change over time/temperature.

rg